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參數(shù)資料
| 型號(hào)： | PI7C8154BNAIE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 59/114頁 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 49 of 114
JUNE 2008 REVISION 1.1
If the prefetchable memory space on the secondary bus resides on top of the 4GB boundary, the
prefetchable memory base address upper 32 bit register is set to 0 and the prefetchable memory
limit address upper 32 bit register is initialized to a nonzero value. Single address cycle memory
transactions are compared to the prefetchable memory base address register only. A transaction
initiated on the primary is forwarded downstream if the address is greater than or equal to the base
address. A transaction initiated on the secondary is forwarded upstream if the address is less than
the base address. Dual address cycles are compared to the prefetchable memory limit address and
the prefetchable memory limit address upper 32 bit register. If the address of the dual address
cycle is less than or equal to the limit, the transaction is forwarded downstream from the primary
and is ignored on the secondary. If the address of the dual address cycle is greater than this limit,
the transaction is ignored on the primary and is forwarded upstream from the secondary.
The prefetchable memory base address upper 32 bit register is located at offset 28h of the
configuration register and the prefetchable memory limit address upper 32 bit register is located at
offset 2Ch. Both registers are reset to 0.
3.4
VGA SUPPORT
PI7C8154B provides two modes for VGA support:
VGA mode, supporting VGA-compatible addressing
VGA snoop mode, supporting VGA palette forwarding
3.4.1
VGA MODE
When a VGA-compatible device exists downstream from PI7C8154B, set the VGA mode bit in the
bridge control register in configuration space to enable VGA mode. When PI7C8154B is operating
in VGA mode, it forwards downstream those transactions addressing the VGA frame buffer
memory and VGA I/O registers, regardless of the values of the base and limit address registers.
PI7C8154B ignores transactions initiated on the secondary interface addressing these locations.
The VGA frame buffer consists of the following memory address range:
000A 0000h–000B FFFFh
Read transactions to frame buffer memory are treated as non-prefetchable. PI7C8154B requests
only a single data transfer from the target, and read byte enable bits are forwarded to the target bus.
The VGA I/O addresses are in the range of 3B0h–3BBh and 3C0h–3DFh I/O. These I/O addresses
are aliases every 1KB throughout the first 64KB of I/O space. This means that address bits [5:10]
are not decoded and can be any value, while address bits [31:16] must be all 0’s. VGA BIOS
addresses starting at C0000h are not decoded in VGA mode.
3.4.2
VGA SNOOP MODE
PI7C8154B provides VGA snoop mode, allowing for VGA palette write transactions to be
forwarded downstream. This mode is used when a graphics device downstream from PI7C8154B
needs to snoop or respond to VGA palette write transactions. To enable the mode, set the VGA
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