Advance Information Page 84 of 114 DEC 2009 REVISION 1.02 14.1.26 CAPABILITY POINTER REGISTER –" />
參數(shù)資料
型號: PI7C8154ANAE
廠商: Pericom
文件頁數(shù): 98/114頁
文件大小: 0K
描述: IC PCI-PCI BRIDGE ASYNC 304-PBGA
標準包裝: 27
系列: *
應用: *
接口: *
電源電壓: *
封裝/外殼: 304-BBGA
供應商設備封裝: 304-PBGA(31x31)
包裝: 管件
安裝類型: 表面貼裝
PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 84 of 114
DEC 2009 REVISION 1.02
14.1.26
CAPABILITY POINTER REGISTER – OFFSET 34h
Bit
Function
Type
Description
7:0
Enhanced
Capabilities Port
Pointer
R/O
Enhanced capabilities port offset pointer. Read as DCh to indicate that
the first item resides at that configuration offset.
Reset to DCh.
14.1.27
INTERRUPT LINE REGISTER – OFFSET 3Ch
Bit
Function
Type
Description
7:0
Interrupt Line
R/W
For POST to program to FFh, indicating that the bridge does not
implement an interrupt pin.
Reset to 0.
14.1.28
INTERRUPT PIN REGISTER – OFFSET 3Ch
Bit
Function
Type
Description
15:8
Interrupt Pin
R/O
Interrupt pin not supported on the bridge.
Reset to 0.
14.1.29
BRIDGE CONTROL REGISTER – OFFSET 3Ch
Bit
Function
Type
Description
16
Parity Error
Response
R/W
Controls the bridge’s response to parity errors on the secondary interface.
0: ignore address and data parity errors on the secondary interface
1: enable parity error reporting and detection on the secondary interface
Reset to 0
17
S_SERR# enable
R/W
Controls the forwarding of S_SERR# to the primary interface.
0: disable the forwarding of S_SERR# to primary interface
1: enable the forwarding of S_SERR# to primary interface
Reset to 0
18
ISA enable
R/W
Modifies the bridge’s response to ISA I/O addresses, applying only to
those addresses falling within the I/O base and limit address registers and
within the first 64KB of PCI I/O space.
0: forward all I/O addresses in the range defined by the I/O base and I/O
limit registers
1: blocks forwarding of ISA I/O addresses in the range defined by the I/O
base and I/O limit registers that are in the first 64KB of I/O space that
address the last 768 bytes in each 1KB block. Secondary I/O transactions
are forwarded upstream if the address falls within the last 768 bytes in
each 1KB block
Reset to 0
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