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| 型號： | PI7C8154ANAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 35/114頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 標準包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 27 of 112
DEC 2009 REVISION 1.02
If the initiator repeats the write transaction before the data has been transferred to the target,
PI7C8154A returns a target retry to the initiator. PI7C8154A continues to return a target retry to
the initiator until write data is delivered to the target, or until an error condition is encountered.
When the write transaction is repeated, PI7C8154A does not make a new entry into the delayed
transaction queue. Section 2.11.3.1 provides detailed information about how PI7C8154A responds
to target termination during delayed write transactions.
PI7C8154A implements a discard timer that starts counting when the delayed write completion is at
the head of the delayed transaction completion queue. The initial value of this timer can be set to
the retry counter register offset 78h.
If the initiator does not repeat the delayed write transaction before the discard timer expires,
PI7C8154A discards the delayed write completion from the delayed transaction completion queue.
PI7C8154A also conditionally asserts P_SERR# (see Section 5.4).
2.6.4
WRITE TRANSACTION ADDRESS BOUNDARIES
PI7C8154A imposes internal address boundaries when accepting write data. The aligned address
boundaries are used to prevent PI7C8154A from continuing a transaction over a device address
boundary and to provide an upper limit on maximum latency. PI7C78154 returns a target
disconnect to the initiator when it reaches the aligned address boundaries under conditions shown
in Table 2-3.
Table 2-3 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES
Type of Transaction
Condition
Aligned Address Boundary
Delayed Write
All
Disconnects after one data transfer
Posted Memory Write
Memory write disconnect control
bit = 0(1)
4KB aligned address boundary
Posted Memory Write
Memory write disconnect control
bit = 1(1)
Disconnects at cache line boundary
Posted Memory Write and
Invalidate
Cache line size
≠ 1, 2, 4, 8, 16
4KB aligned address boundary
Posted Memory Write and
Invalidate
Cache line size = 1, 2, 4, 8
Cache line boundary if posted memory write data
FIFO does not have enough space for the next
cache line
Posted Memory Write and
Invalidate
Cache line size = 16
16-DWORD aligned address boundary
Note 1. Memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the configuration space.
2.6.5
BUFFERING MULTIPLE WRITE TRANSACTIONS
PI7C8154A continues to accept posted memory write transactions as long as space for at least one
DWORD of data in the posted write data buffer remains. If the posted write data buffer fills before
the initiator terminates the write transaction, PI7C8154A returns a target disconnect to the initiator.
Delayed write transactions are accepted as long as at least one open entry in the delayed transaction
queue exists. Therefore, several posted and delayed write transactions can exist in data buffers at
the same time. See Chapter 4 for information about how multiple posted and delayed write
transactions are ordered.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154ANAE-33 | 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
| PI7C8154BNA | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAE | 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154BNAE-80 | 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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