- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1961 > PI7C8154ANAE (Pericom)IC PCI-PCI BRIDGE ASYNC 304-PBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | PI7C8154ANAE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 79/114頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)當(dāng)前第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)
PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 67 of 114
DEC 2009 REVISION 1.02
7.2.3
SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER
The internal arbiter is disabled when the secondary bus central function control pin, S_CFN#, is
tied HIGH. An external arbiter must then be used.
When S_CFN# is tied HIGH, PI7C8154A reconfigures two pins to be external request and grant
pins. The S_GNT#[0] pin is reconfigured to be the external request pin because it’s an output. The
S_REQ#[0] pin is reconfigured to be the external grant pin because it’s an input. When an external
arbiter is used, PI7C8154A uses the S_GNT#[0] pin to request the secondary bus. When the
reconfigured S_REQ#[0] pin is asserted LOW after PI7C8154A has asserted S_GNT#[0],
PI7C8154A initiates a transaction on the secondary bus one cycle later. If grant is asserted and
PI7C8154A has not asserted the request, PI7C8154A parks AD, CBE and PAR pins by driving
them to valid logic levels.
The unused secondary bus grant outputs, S_GNT#[8:1] are driven HIGH. The unused secondary
bus request inputs, S_REQ#[8:1], should be pulled HIGH.
7.2.4
BUS PARKING
Bus parking refers to driving the AD[31:0], CBE[3:0], and PAR lines to a known value while the
bus is idle. In general, the device implementing the bus arbiter is responsible for parking the bus or
assigning another device to park the bus. A device parks the bus when the bus is idle, its bus grant
is asserted, and the device’s request is not asserted. The AD[31:0] and CBE[3:0] signals should be
driven first, with the PAR signal driven one cycle later. The AD[63:32] and CBE[7:4] are not
driven and need to be pulled up to a valid logic level through external resistors.
PI7C8154A parks the primary bus only when P_GNT# is asserted, P_REQ# is de-asserted, and the
primary PCI bus is idle. When P_GNT# is de-asserted, PI7C8154A 3-states the P_AD, P_CBE, and
P_PAR signals on the next PCI clock cycle. If PI7C8154A is parking the primary PCI bus and
wants to initiate a transaction on that bus, then PI7C8154A can start the transaction on the next PCI
clock cycle by asserting P_FRAME# if P_GNT# is still asserted.
If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last
master that used the PCI bus. That is, PI7C8154A keeps the secondary bus grant asserted to a
particular master until a new secondary bus request comes along. After reset, PI7C8154A parks the
secondary bus at itself until transactions start occurring on the secondary bus. Offset 48h, bit 1, can
be set to 1 to park the secondary bus at PI7C8154A. By default, offset 48h, bit 1, is set to 0. If the
internal arbiter is disabled, PI7C8154A parks the secondary bus only when the reconfigured grant
signal, S_REQ#[0], is asserted and the secondary bus is idle.
8
GENERAL PURPOSE I/O INTERFACE
The PI7C8154A implements a 4-pin general purpose I/O interface. During normal operation,
device specific configuration registers control the GPIO interface. The GPIO interface can be used
for the following functions:
During secondary interface reset, the GPIO interface can be used to shift in a 16-bit serial
stream that serves as a secondary bus clock disable mask.
Along with the GPIO[3] pin, a live insertion bit can be used to bring the PI7C8154A to a halt
through hardware, permitting live insertion of option cards behind the PI7C8154A.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8154BNAIE | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| PI7C9X110BNBE | IC PCIE TO PCI REV BRG 160LFBGA |
| PI7C9X130DNDE | IC PCIE-PCIX BRIDGE 1PORT 256BGA |
| PI7C9X20303SLCFDE | IC PCIE PACKET SWITCH 128LQFP |
| PI7C9X20303ULAZPE | IC PCIE PACKET SWITCH 132TQFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154ANAE-33 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
| PI7C8154BNA | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154BNAE-80 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。