Advance Information Page 39 of 112 DEC 2009 REVISION 1.02 status register when the master abort" />
參數(shù)資料
型號(hào): PI7C8154ANAE
廠商: Pericom
文件頁數(shù): 48/114頁
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE ASYNC 304-PBGA
標(biāo)準(zhǔn)包裝: 27
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 304-BBGA
供應(yīng)商設(shè)備封裝: 304-PBGA(31x31)
包裝: 管件
安裝類型: 表面貼裝
PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 39 of 112
DEC 2009 REVISION 1.02
status register when the master abort is received on the secondary interface. When master abort is
detected in posted write transaction with both master-abort-mode bit (bit[5] of bridge control
register) and the SERR# enable bit (bit 8 of command register for secondary bus) are set,
PI7C8154A asserts P_SERR# if the master-abort-on-posted-write is not set. The master-abort-on-
posted-write bit is bit 4 of the P_SERR# event disable register (offset 64h).
Note: When PI7C8154A performs a Type 1 to special cycle conversion, a master abort is the
expected termination for the special cycle on the target bus. In this case, the master abort received
bit is not set, and the Type 1 configuration transaction is disconnected after the first data phase.
2.11.3
TARGET TERMINATION RECEIVED BY PI7C8154A
When PI7C8154A initiates a transaction on the target bus and the target responds with DEVSEL#,
the target can end the transaction with one of the following types
of termination:
Normal termination (upon de-assertion of FRAME#)
Target retry
Target disconnect
Target abort
PI7C8154A handles these terminations in different ways, depending on the type of transaction
being performed.
2.11.3.1
DELAYED WRITE TARGET TERMINATION RESPONSE
When PI7C8154A initiates a delayed write transaction, the type of target termination received from
the target can be passed back to the initiator.
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