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參數(shù)資料
| 型號(hào)： | PI7C8154ANAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 81/114頁 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 69 of 114
DEC 2009 REVISION 1.02
Table 8-1 GPIO OPERATION
GPIO Pin
Operation
GPIO[0]
Shift register clock output at 33MHz max frequency
GPIO[1]
Not used
GPIO[2]
Shift register control
0: Load
1: Shift
GPIO[3]
Not used
The data is input through the dedicated input signal, MSK_IN.
The shift register circuitry is not necessary for correct operation of PI7C8154A. The shift register
can be eliminated, and MSK_IN can be tied LOW to enable all secondary clock outputs or tied
HIGH to force all secondary clock outputs HIGH. Table 8-2 shows the format of the serial stream.
Table 8-2 GPIO SERIAL DATA FORMAT
Bit
Description
S_CLKOUT
[1:0]
Slot 0 PRSNT#[1:0] or device 0
0
[3:2]
Slot 1 PRSNT#[1:0] or device 1
1
[5:4]
Slot 2 PRSNT#[1:0] or device 2
2
[7:6]
Slot 3 PRSNT#[1:0] or device 3
3
[8]
Device 4
4
[9]
Device 5
5
[10]
Device 6
6
[11]
Device 7
7
[12]
Device 8
8
[13]
PI7C8154A S_CLKIN
9
[14]
Reserved
NA
[15]
Reserved
NA
The first 8 bits contain the PRSNT#[1:0] signal values for four slots, and these bits control the
S_CLKOUT[3:0] outputs. If one or both of the PRSNT#[1:0] signals are 0, that indicates that a
card is present in the slot and therefore the secondary clock for that slot is not masked. If these
clocks are connected to devices and not to slots, one or both of the bits should be tied low to enable
the clock.
The next 5 bits are the clock mask for devices; each bit enables or disables the clock for one device.
These bits control the S_CLKOUT[8:4] outputs: 0 enables the clock, and 1 disables the clock.
Bit 13 is the clock enable bit for S_CLKOUT[9], which is connected to PI7C8154A’s S_CLKIN
input.
If desired, the assignment of S_CLKOUT outputs to slots, devices, and PI7C8154A’s S_CLKIN
input can be rearranged from the assignment shown here. However, it is important that the serial
data stream format match the assignment of S_CLKOUT.
The 8 least significant bits are connected to the PRSNT# pins for the slots. The next 5 bits are tied
high to disable their respective secondary clocks because those clocks are not connected to
anything. The next bit is tied LOW because that secondary clock output is connected to the bridge
S_CLKIN input. When the secondary reset signal, S_RESET#, is detected asserted and the primary
reset signal, P_RESET#, is detected deasserted, the bridge drives GPIO[2] LOW for one cycle to
load the clock mask inputs into the shift register. On the next cycle, PI7C8154A drives GPIO[2]
HIGH to perform a shift operation. This shifts the clock mask into MSK_IN; the most significant
bit is shifted in first, and the least significant bit is shifted in last.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154ANAE-33 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
| PI7C8154BNA | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154BNAE-80 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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