- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1961 > PI7C8154ANAE (Pericom)IC PCI-PCI BRIDGE ASYNC 304-PBGA PDF資料下載
參數(shù)資料
| 型號： | PI7C8154ANAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 68/114頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 標準包裝： | 27 |
| 系列： | * |
| 應用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應商設備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁當前第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁
PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 57 of 114
DEC 2009 REVISION 1.02
Bridge completes the transaction normally.
For upstream transactions, when the parity error is being passed back from the target bus and the
parity error condition was not originally detected on the initiator bus, the following events occur:
Bridge asserts S_PERR# two cycles after the data transfer, if the following are both true:
The parity error response bit is set in the command register of the primary interface.
The parity error response bit is set in the bridge control register of the secondary interface.
Bridge completes the transaction normally.
5.2.4
POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when the bridge responds as a target, it detects a data
parity error on the initiator (primary) bus and the following events occur:
Bridge asserts P_PERR# two cycles after the data transfer, if the parity error response bit is set
in the command register of primary interface.
Bridge sets the parity error detected bit in the status register of the primary interface.
Bridge captures and forwards the bad parity condition to the secondary bus.
Bridge completes the transaction normally.
Similarly, during upstream posted write transactions, when the bridge responds as a target, it
detects a data parity error on the initiator (secondary) bus, the following events occur:
Bridge asserts S_PERR# two cycles after the data transfer, if the parity error response bit is set
in the bridge control register of the secondary interface.
Bridge sets the parity error detected bit in the status register of the secondary interface.
Bridge captures and forwards the bad parity condition to the primary bus.
Bridge completes the transaction normally.
During downstream write transactions, when a data parity error is reported on the target
(secondary) bus by the target’s assertion of S_PERR#, the following events occur:
Bridge sets the data parity detected bit in the status register of secondary interface, if the parity
error response bit is set in the bridge control register of the secondary interface.
Bridge asserts P_SERR# and sets the signaled system error bit in the status register, if all the
following conditions are met:
The SERR# enable bit is set in the command register.
The posted write parity error bit of P_SERR# event disable register is not set.
The parity error response bit is set in the bridge control register of the secondary interface.
The parity error response bit is set in the command register of the primary interface.
Bridge has not detected the parity error on the primary (initiator) bus which the parity
error is not forwarded from the primary bus to the secondary bus.
During upstream write transactions, when a data parity error is reported on the target (primary) bus
by the target’s assertion of P_PERR#, the following events occur:
相關PDF資料 |
PDF描述 |
|---|---|
| PI7C8154BNAIE | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| PI7C9X110BNBE | IC PCIE TO PCI REV BRG 160LFBGA |
| PI7C9X130DNDE | IC PCIE-PCIX BRIDGE 1PORT 256BGA |
| PI7C9X20303SLCFDE | IC PCIE PACKET SWITCH 128LQFP |
| PI7C9X20303ULAZPE | IC PCIE PACKET SWITCH 132TQFN |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154ANAE-33 | 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
| PI7C8154BNA | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAE | 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154BNAE-80 | 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。