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參數(shù)資料
| 型號(hào)： | PI7C8154ANAE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 19/114頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類(lèi)型： | 表面貼裝 |
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PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 12 of 112
DEC 2009 REVISION 1.02
1
SIGNAL DEFINITIONS
1.1
SIGNAL TYPES
Signal Type
Description
I
Input Only
O
Output Only
P
Power
TS
Tri-State bi-directional
STS
Sustained Tri-State. Active LOW signal must be pulled HIGH for 1 cycle when deasserting.
OD
Open Drain
1.2
SIGNALS
Note: Signal names that end with “#” are active LOW.
1.2.1
PRIMARY BUS INTERFACE SIGNALS
Name
Pin #
Type
Description
P_AD[31:0]
U2, U4, U1, V2, V1, V3,
W2, W1, W4, Y3, AA1,
AA3, Y4, AB3, AA4, Y5,
AB8, AA8, AC9, AB9,
AA9, AC10, AA10, Y11,
AB11, AA11, AA12, AB12,
AB13, AA13, Y13, AA14
TS
Primary Address / Data: Multiplexed address and
data bus. Address is indicated by P_FRAME#
assertion. Write data is stable and valid when
P_IRDY# is asserted and read data is stable and
valid when P_TRDY# is asserted. Data is
transferred on rising clock edges when both
P_IRDY# and P_TRDY# are asserted. During bus
idle, bridge drives P_AD[31:0] to a valid logic level
when P_GNT# is asserted.
P_CBE[3:0]
Y2, AB4, AA7, AC11
TS
Primary Command/Byte Enables: Multiplexed
command field and byte enable field. During
address phase, the initiator drives the transaction
type on these pins. After that, the initiator drives the
byte enables during data phases. During bus idle,
bridge drives P_CBE[3:0] to a valid logic level
when P_GNT# is asserted.
P_PAR
AB7
TS
Primary Parity. P_PAR is even parity of
P_AD[31:0] and P_CBE[3:0] (i.e. an even number
of 1’s). P_PAR is valid and stable one cycle after
the address phase (indicated by assertion of
P_FRAME#) for address parity. For write data
phases, P_PAR is valid one clock after P_IRDY# is
asserted. For read data phase, P_PAR is valid one
clock after P_TRDY# is asserted. Signal P_PAR is
tri-stated one cycle after the P_AD lines are tri-
stated. During bus idle, BRIDGE drives P_PAR to
a valid logic level when P_GNT# is asserted.
P_FRAME#
AA5
STS
Primary FRAME (Active LOW). Driven by the
initiator of a transaction to indicate the beginning
and duration of an access. The de-assertion of
P_FRAME# indicates the final data phase requested
by the initiator. Before being tri-stated, it is driven
to a de-asserted state for one cycle.
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| PI7C8154ANAE-33 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
| PI7C8154BNA | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154BNAE-80 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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