Advance Information Page 23 of 112 DEC 2009 REVISION 1.02 2 SIGNAL DEFINITIONS This Chapter off" />
參數(shù)資料
型號: PI7C8154ANAE
廠商: Pericom
文件頁數(shù): 31/114頁
文件大小: 0K
描述: IC PCI-PCI BRIDGE ASYNC 304-PBGA
標(biāo)準(zhǔn)包裝: 27
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 304-BBGA
供應(yīng)商設(shè)備封裝: 304-PBGA(31x31)
包裝: 管件
安裝類型: 表面貼裝
PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 23 of 112
DEC 2009 REVISION 1.02
2
SIGNAL DEFINITIONS
This Chapter offers information about PCI transactions, transaction forwarding across PI7C8154A,
and transaction termination. The PI7C8154A has two 128-byte buffers for read data buffering of
upstream and downstream transactions. Also, PI7C8154A has two 128-byte buffers for write data
buffering of upstream and downstream transactions.
2.1
TYPES OF TRANSACTIONS
This section provides a summary of PCI transactions performed by PI7C8154A. Table 2-1 lists the
command code and name of each PCI transaction. The Master and Target columns indicate support
for each transaction when PI7C8154A initiates transactions as a master, on the primary and
secondary buses, and when PI7C8154A responds to transactions as a target, on the primary and
secondary buses.
Table 2-1 PCI TRANSACTIONS
Types of Transactions
Initiates as Master
Responds as Target
Primary
Secondary
Primary
Secondary
0000
Interrupt Acknowledge
N
0001
Special Cycle
Y
N
0010
I/O Read
Y
0011
I/O Write
Y
0100
Reserved
N
0101
Reserved
N
0110
Memory Read
Y
0111
Memory Write
Y
1000
Reserved
N
1001
Reserved
N
1010
Configuration Read
N
Y
N
1011
Configuration Write
Y (Type 1 only)
Y
Y (Type 1 only)
1100
Memory Read Multiple
Y
1101
Dual Address Cycle
Y
1110
Memory Read Line
Y
1111
Memory Write and Invalidate
Y
As indicated in Table 2-1, the following PCI commands are not supported by PI7C8154A:
PI7C8154A never initiates a PCI transaction with a reserved command code and, as a target,
PI7C8154A ignores reserved command codes.
PI7C8154A does not generate interrupt acknowledge transactions. PI7C8154A ignores
interrupt acknowledge transactions as a target.
PI7C8154A does not respond to special cycle transactions. PI7C8154A cannot guarantee
delivery of a special cycle transaction to downstream buses because of the broadcast nature of
the special cycle command and the inability to control the transaction as a target. To generate
special cycle transactions on other PCI buses, either upstream or downstream, Type 1
configuration write must be used.
PI7C8154A neither generates Type 0 configuration transactions on the primary PCI bus nor
responds to Type 0 configuration transactions on the secondary PCI bus.
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