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PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 73 of 114
DEC 2009 REVISION 1.02
Support for D0, D1, D2, D3HOT, and D3COLD power management states for devices behind the
bridge
Support of the B2 secondary bus power state when in the D3HOT power management state
Table 12-1 shows the states and related actions that the bridge performs during power management
transitions. (No other transactions are permitted.)
Table 12-1 POWER MANAGEMENT TRANSITIONS
Current Status
Next State
Action
D0
D3COLD
Power has been removed from PI7C8154A. A power-up reset must be
performed to bring PI7C8154A to D0.
D0
D3HOT
If enabled to do so by the BPCCE pin, PI7C8154A will disable the
secondary clocks and drive them LOW.
D0
D2
Unimplemented. PI7C8154A will ignore the write to the power state bits.
Power state will remain at D0.
D0
D1
Unimplemented. PI7C8154A will ignore the write to the power state bits.
Power state will remain at D0.
D3HOT
D0
PI7C8154A enables secondary clock outputs and performs an internal
chip reset. Signal S_RST# will not be asserted. All registers will be
returned to the reset values and buffers will be cleared.
D3COLD
Power has been removed from PI7C8154A. A power-up reset must be
performed to bring PI7C8154A to D0.
D3COLD
D0
Power-up reset. PI7C8154A performs the standard power-up reset
functions as described in Section 11.
PME# signals are routed from downstream devices around PCI-to-PCI bridges. PME# signals do
not pass through PCI-to-PCI bridges.