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| 型號(hào)： | PI7C8154ANAE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 106/114頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類(lèi)型： | 表面貼裝 |
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PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 91 of 114
DEC 2009 REVISION 1.02
Bit
Function
Type
Description
1
Posted Write
with Parity Error
R/W
0: P_SERR# is asserted if a parity error is detected on the target bus
during a posted write transaction and the SERR# enable bit in the
command register is set.
1: P_SERR# is not asserted, although a parity error is detected on the
target bus during a posted write transaction and the SERR# enable bit in
the command register is set.
Reset to 0
2
Posted Write
with Non-
Delivery Data
R/W
0: P_SERR# is asserted if the bridge is not able to transfer any posted
write data after 224 attempts and the SERR# enable bit in the command
register is set.
1: P_SERR# is not asserted although the bridge is not able to transfer any
posted write data after 224 attempts and the SERR# enable bit in the
command register is set.
Reset to 0
3
Target Abort
During Posted
Write
R/W
0: P_SERR# is asserted if the bridge receives a target abort when
attempting to deliver posted write data and the SERR# enable bit in the
command register is set.
1: P_SERR# is not asserted even though the bridge receives a target
abort when attempting to deliver posted write data and the SERR# enable
bit in the command register is set.
Reset to 0
4
Master Abort
During Posted
Write
R/W
0: P_SERR# is asserted if the bridge receives a master abort when
attempting to deliver posted write data and the SERR# enable bit in the
command register is set.
1: P_SERR# is not asserted even though the bridge receives a master
abort when attempting to deliver posted write data and the SERR# enable
bit in the command register is set.
Reset to 0
5
Delayed Write
with Non-
Delivery
R/W
0: P_SERR# is asserted if the bridge is not able to transfer any delayed
write data after 224 attempts and the SERR# enable bit in the command
register is set.
1: P_SERR# is not asserted even though the bridge is not able to transfer
any delayed write data after 224 attempts and the SERR# enable bit in the
command register is set.
Reset to 0
6
Delayed Read
Without Data
From Target
R/W
0: P_SERR# is asserted if the bridge is not able to transfer any read data
from the target after 224 attempts and the SERR# enable bit in the
command register is set.
1: P_SERR# is not asserted even though the bridge is not able to transfer
and read data from the target after 224 attempts and the SERR# enable bit
in the command register is set.
Reset to 0.
7
Reserved
R/O
Returns 0 when read. Reset to 0.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154ANAE-33 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
| PI7C8154BNA | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154BNAE-80 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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