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參數(shù)資料
| 型號(hào)： | PI7C8154ANAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 61/114頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 50 of 114
DEC 2009 REVISION 1.02
snoop bit in the command register in configuration space. Note that PI7C8154A claims VGA
palette write transactions by asserting DEVSEL# in VGA snoop mode.
When VGA snoop bit is set, PI7C8154A forwards downstream transactions within the 3C6h, 3C8h
and 3C9h I/O addresses space. Note that these addresses are also forwarded as part of the VGA
compatibility mode previously described. Again, address bits [15:10] are not decoded, while
address bits [31:16] must be equal to 0, which means that these addresses are aliases every 1KB
throughout the first 64KB of I/O space.
Note: If both the VGA mode bit and the VGA snoop bit are set, PI7C8154A behaves in the same
way as if only the VGA mode bit were set.
4
TRANSACTION ORDERING
To maintain data coherency and consistency, PI7C8154A complies with the ordering rules set forth
in the PCI Local Bus Specification, Revision 2.2, for transactions crossing the bridge. This chapter
describes the ordering rules that control transaction forwarding across PI7C8154A.
4.1
TRANSACTIONS GOVERNED BY ORDERING RULES
Ordering relationships are established for the following classes of transactions crossing
PI7C8154A:
Posted write transactions, comprised of memory write and memory write and invalidate
transactions.
Posted write transactions complete at the source before they complete at the destination; that is,
data is written into intermediate data buffers before it reaches the target.
Delayed write request transactions, comprised of I/O write and configuration write
transactions.
Delayed write requests are terminated by target retry on the initiator bus and are queued in the
delayed transaction queue. A delayed write transaction must complete on the target bus before it
completes on the initiator bus.
Delayed write completion transactions, comprised of I/O write and configuration write
transactions.
Delayed write completion transactions complete on the target bus, and the target response is queued
in the buffers. A delayed write completion transaction proceeds in the direction opposite that of the
original delayed write request; that is, a delayed write completion transaction proceeds from the
target bus to the initiator bus.
Delayed read request transactions, comprised of all memory read, I/O read, and
configuration read transactions.
Delayed read requests are terminated by target retry on the initiator bus and are queued in the
delayed transaction queue.
Delayed read completion transactions, comprised of all memory read, I/O read, &
configuration read transactions.
Delayed read completion transactions complete on the target bus, and the read data is queued in the
read data buffers. A delayed read completion transaction proceeds in the direction opposite that of
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154ANAE-33 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
| PI7C8154BNA | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154BNAE-80 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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