- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1961 > PI7C8154ANAE (Pericom)IC PCI-PCI BRIDGE ASYNC 304-PBGA PDF資料下載
參數(shù)資料
| 型號： | PI7C8154ANAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 77/114頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁當(dāng)前第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁
PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 65 of 114
DEC 2009 REVISION 1.02
secondary PCI bus, the bridge implements an internal arbiter. This arbiter can be disabled, and an
external arbiter can be used instead. This chapter describes primary and secondary bus arbitration.
7.1
PRIMARY PCI BUS ARBITRATION
The bridge implements a request output pin, P_REQ#, and a grant input pin, P_GNT#, for primary
PCI bus arbitration. The bridge asserts P_REQ# when forwarding transactions upstream; that is, it
acts as initiator on the primary PCI bus. As long as at least one pending transaction resides in the
queues in the upstream direction, either posted write data or delayed transaction requests, the
bridge keeps P_REQ# asserted. However, if a target retry, target disconnect, or a target abort is
received in response to a transaction initiated by the bridge on the primary PCI bus, the bridge de-
asserts P_REQ# for two PCI clock cycles.
For all cycles through the bridge, P_REQ# is not asserted until the transaction request has been
completely queued. When P_GNT# is asserted LOW by the primary bus arbiter after the bridge
has asserted P_REQ#, PI7C8154A initiates a transaction on the primary bus during the next PCI
clock cycle. When P_GNT# is asserted to PI7C8154A when P_REQ# is not asserted, the bridge
parks P_AD, P_CBE, and P_PAR by driving them to valid logic levels. When the primary bus is
parked at the bridge and the bridge has a transaction to initiate on the primary bus, the bridge starts
the transaction if P_GNT# was asserted during the previous cycle.
7.2
SECONDARY PCI BUS ARBITRATION
The bridge implements an internal secondary PCI bus arbiter. This arbiter supports eight external
masters on the secondary bus in addition to PI7C8154A. The internal arbiter can be disabled, and
an external arbiter can be used instead for secondary bus arbitration.
7.2.1
SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER
To use the internal arbiter, the secondary bus arbiter enable pin, S_CFN#, must be tied LOW.
PI7C8154A has nine secondary bus request input pins, S_REQ#[8:0], and has nine secondary bus
output grant pins, S_GNT#[8:0], to support external secondary bus masters.
The secondary bus request and grant signals are connected internally to the arbiter and are not
brought out to external pins when S_CFN# is LOW.
The secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with each set
taking care of 4 requests / grants. Each set of masters can be assigned to a high priority group and a
low priority group. The low priority group as a whole represents one entry in the high priority
group; that is, if the high priority group consists of n masters, then in at least every n+1 transactions
the highest priority is assigned to the low priority group. Priority rotates evenly among the low
priority group. Therefore, members of the high priority group can be serviced n transactions out of
n+1, while one member of the low priority group is serviced once every n+1 transactions. Figure
7-1 shows an example of an internal arbiter where four masters, including the bridge, are in the
high priority group, and five masters are in the low priority group. Using this example, if all
requests are always asserted, the highest priority rotates among the masters in the following fashion
(high priority members are given in italics, low priority members, in boldface type): B, m0, m1, m2,
m3, B, m0, m1, m2, m4, B, m0, m1, m2, m5, B, m0, m1, m2, m6 and so on.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8154BNAIE | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| PI7C9X110BNBE | IC PCIE TO PCI REV BRG 160LFBGA |
| PI7C9X130DNDE | IC PCIE-PCIX BRIDGE 1PORT 256BGA |
| PI7C9X20303SLCFDE | IC PCIE PACKET SWITCH 128LQFP |
| PI7C9X20303ULAZPE | IC PCIE PACKET SWITCH 132TQFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154ANAE-33 | 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
| PI7C8154BNA | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAE | 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154BNAE-80 | 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。