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參數(shù)資料
| 型號： | PI7C8154ANAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 37/114頁 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 標準包裝： | 27 |
| 系列： | * |
| 應用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應商設備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 29 of 112
DEC 2009 REVISION 1.02
2.7.3
READ PREFETCH ADDRESS BOUNDARIES
PI7C8154A imposes internal read address boundaries on read prefetched data. When a read
transaction reaches one of these aligned address boundaries, the PI7C8154A stops pre-fetched data,
unless the target signals a target disconnect before the read prefetched boundary is reached. When
PI7C8154A finishes transferring this read data to the initiator, it returns a target disconnect with the
last data transfer, unless the initiator completes the transaction before all pre-fetched read data is
delivered. Any leftover pre-fetched data is discarded.
Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB address
boundary, or until the initiator de-asserts FRAME#. Section 2.7.6 describes flow-through mode
during read operations.
Table 2-4 shows the read pre-fetch address boundaries for read transactions during non-flow-
through mode.
Table 2-4 READ PREFETCH ADDRESS BOUNDARIES
Type of Transaction
Address Space
Cache Line Size
(CLS)
Prefetch Aligned Address Boundary
Configuration Read
-
*
One DWORD (no prefetch)
I/O Read
-
*
One DWORD (no prefetch)
Memory Read
Non-Prefetchable
*
One DWORD (no prefetch)
Memory Read
Prefetchable
CLS = 0 or 16
16-DWORD aligned address boundary
Memory Read
Prefetchable
CLS = 1, 2, 4, 8
Cache line address boundary
Memory Read Line
-
CLS = 0 or 16
16-DWORD aligned address boundary
Memory Read Line
-
CLS = 1, 2, 4, 8
Cache line boundary
Memory Read Multiple
-
CLS = 0 or 16
Queue full
Memory Read Multiple
-
CLS = 1, 2, 4, 8
Second cache line boundary
- does not matter if it is prefetchable or non-prefetchable
* don’t care
Table 2-5 READ TRANSACTION PREFETCHING
Type of Transaction
Read Behavior
I/O Read
Prefetching never allowed
Configuration Read
Prefetching never allowed
Downstream: Prefetching used if address is prefetchable space
Memory Read
Upstream: Prefetching used or programmable
Memory Read Line
Prefetching always used
Memory Read Multiple
Prefetching always used
See Section 3.3 for detailed information about prefetchable and non-prefetchable address spaces.
2.7.4
DELAYED READ REQUESTS
PI7C8154A treats all read transactions as delayed read transactions, which means that the read
request from the initiator is posted into a delayed transaction queue. Read data from the target is
placed in the read data queue directed toward the initiator bus interface and is transferred to the
initiator when the initiator repeats the read transaction.
PI7C8154A accepts a delayed read request, by sampling the read address, read bus command, and
address parity. When IRDY# is asserted, PI7C8154A then samples the byte enable bits for the first
data phase. This information is entered into the delayed transaction queue. PI7C8154A terminates
the transaction by signaling a target retry to the initiator. Upon reception of the target retry, the
initiator is required to continue to repeat the same read transaction until at least one data transfer is
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154ANAE-33 | 功能描述:外圍驅動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
| PI7C8154BNA | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAE | 功能描述:外圍驅動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154BNAE-80 | 功能描述:外圍驅動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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