Advance Information Page 59 of 114 DEC 2009 REVISION 1.02 Secondary Detected Parity Error Bit T" />
參數(shù)資料
型號： PI7C8154ANAE
廠商： Pericom
文件頁數(shù)： 70/114頁
文件大小： 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
標準包裝： 27
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應(yīng)商設(shè)備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類型： 表面貼裝
PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 59 of 114
DEC 2009 REVISION 1.02
Secondary
Detected Parity
Error Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/ Secondary Parity
Error Response Bits
0
Read
Upstream
Primary
x / x
0
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
x / x
0
Posted Write
Downstream
Secondary
x / x
0
Posted Write
Upstream
Primary
x / x
1
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
x / x
0
Delayed Write
Downstream
Secondary
x / x
0
Delayed Write
Upstream
Primary
x / x
1
Delayed Write
Upstream
Secondary
x / x
Note: x=don’t care
Table 5-3 shows setting data parity detected bit in the primary interface’s status register. This bit is
set under the following conditions:
PI7C8154A must be a master on the primary bus.
The parity error response bit in the command register, corresponding to the primary interface,
must be set.
The P_PERR# signal is detected asserted or a parity error is detected on the primary bus.
Table 5-3 SETTING THE PRIMARY INTERFACE DATA PARITY DETECTED BIT (bit
24 of offset 04h)
Primary Data
Parity Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary / Secondary Parity
Error Response Bits
0
Read
Downstream
Primary
x / x
0
Read
Downstream
Secondary
x / x
1
Read
Upstream
Primary
1 / x
0
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
x / x
0
Posted Write
Downstream
Secondary
x / x
1
Posted Write
Upstream
Primary
1 / x
0
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
x / x
0
Delayed Write
Downstream
Secondary
x / x
1
Delayed Write
Upstream
Primary
1 / x
0
Delayed Write
Upstream
Secondary
x / x
Note: x=don’t care
Table 5-4 shows setting the data parity detected bit in the status register of secondary interface.
This bit is set under the following conditions:
The PI7C8154A must be a master on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary interface.
The S_PERR# signal is detected asserted or a parity error is detected on the secondary bus.
Table 5-4 SETTING THE SECONDARY INTERFACE DATA PARITY DETECTED BIT
Secondary
Detected Parity
Detected Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary / Secondary Parity
Error Response Bits
0
Read
Downstream
Primary
x / x
1
Read
Downstream
Secondary
x / 1
0
Read
Upstream
Primary
x / x
0
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
x / x
1
Posted Write
Downstream
Secondary
x / 1
相關(guān)PDF資料
PDF描述
PI7C8154BNAIE IC PCI-PCI BRIDGE ASYNC 304-PBGA
PI7C9X110BNBE IC PCIE TO PCI REV BRG 160LFBGA
PI7C9X130DNDE IC PCIE-PCIX BRIDGE 1PORT 256BGA
PI7C9X20303SLCFDE IC PCIE PACKET SWITCH 128LQFP
PI7C9X20303ULAZPE IC PCIE PACKET SWITCH 132TQFN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C8154ANAE-33 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8154B 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE
PI7C8154BNA 制造商:Pericom Semiconductor Corporation 功能描述:
PI7C8154BNAE 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8154BNAE-80 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*