- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1961 > PI7C8154ANAE (Pericom)IC PCI-PCI BRIDGE ASYNC 304-PBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | PI7C8154ANAE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 33/114頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)當(dāng)前第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)
PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 25 of 112
DEC 2009 REVISION 1.02
2.6
WRITE TRANSACTIONS
Write transactions are treated as either posted write or delayed write transactions. Table 2-2 shows
the method of forwarding used for each type of write operation.
Table 2-2 WRITE TRANSACTION FORWARDING
Type of Transaction
Type of Forwarding
Memory Write
Posted (except VGA memory)
Memory Write and Invalidate
Posted
Memory Write to VGA memory
Delayed
I/O Write
Delayed
Type 1 Configuration Write
Delayed
2.6.1
MEMORY WRITE TRANSACTIONS
Posted write forwarding is used for “Memory Write” and “Memory Write and Invalidate”
transactions.
When PI7C8154A determines that a memory write transaction is to be forwarded across the bridge,
PI7C8154A asserts DEVSEL# with medium decode timing and TRDY# in the next cycle, provided
that enough buffer space is available in the posted memory write queue for the address and at least
one DWORD of data. Under this condition, PI7C8154A accepts write data without obtaining
access to the target bus. The PI7C8154A can accept one DWORD of write data every PCI clock
cycle. That is, no target wait state is inserted. The write data is stored in an internal posted write
buffers and is subsequently delivered to the target. The PI7C8154A continues to accept write data
until one of the following events occurs:
The initiator terminates the transaction by de-asserting FRAME# and IRDY#.
An internal write address boundary is reached, such as a cache line boundary or an aligned
4KB boundary, depending on the transaction type.
The posted write data buffer fills up.
When one of the last two events occurs, the PI7C8154A returns a target disconnect to the
requesting initiator on this data phase to terminate the transaction.
Once the posted write data moves to the head of the posted data queue, PI7C8154A asserts its
request on the target bus. This can occur while PI7C8154A is still receiving data on the initiator
bus. When the grant for the target bus is received and the target bus is detected in the idle
condition, PI7C8154A asserts FRAME# and drives the stored write address out on the target bus.
On the following cycle, PI7C8154A drives the first DWORD of write data and continues to transfer
write data until all write data corresponding to that transaction is delivered, or until a target
termination is received. As long as write data exists in the queue, PI7C8154A can drive one
DWORD of write data in each PCI clock cycle; that is, no master wait states are inserted. If write
data is flowing through PI7C8154A and the initiator stalls, PI7C8154A will signal the last data
phase for the current transaction at the target bus if the queue empties. PI7C8154A will restart the
follow-on transactions if the queue has new data.
PI7C8154A ends the transaction on the target bus when one of the following conditions is met:
All posted write data has been delivered to the target.
The target returns a target disconnect or target retry (PI7C8154A starts another transaction to
deliver the rest of the write data).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8154BNAIE | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| PI7C9X110BNBE | IC PCIE TO PCI REV BRG 160LFBGA |
| PI7C9X130DNDE | IC PCIE-PCIX BRIDGE 1PORT 256BGA |
| PI7C9X20303SLCFDE | IC PCIE PACKET SWITCH 128LQFP |
| PI7C9X20303ULAZPE | IC PCIE PACKET SWITCH 132TQFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154ANAE-33 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
| PI7C8154BNA | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154BNAE-80 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。