Advance Information Page 61 of 114 DEC 2009 REVISION 1.02 S_PERR# Transaction Type Direction Bu" />
參數(shù)資料
型號(hào)： PI7C8154ANAE
廠商： Pericom
文件頁數(shù)： 73/114頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
標(biāo)準(zhǔn)包裝： 27
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應(yīng)商設(shè)備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類型： 表面貼裝
PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 61 of 114
DEC 2009 REVISION 1.02
S_PERR#
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/ Secondary Parity
Error Response Bits
1
Delayed Write
Downstream
Secondary
x / x
02
Delayed Write
Upstream
Primary
1 / 1
0
Delayed Write
Upstream
Secondary
x / 1
Note: x=don’t care
2
=The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Table 5-7 shows assertion of P_SERR#. This signal is set under the following conditions:
PI7C8154A has detected P_PERR# asserted on an upstream posted write transaction or
S_PERR# asserted on a downstream posted write transaction.
PI7C8154A did not detect the parity error as a target of the posted write transaction.
The parity error response bit on the command register and the parity error response bit on the
bridge control register must both be set.
The SERR# enable bit must be set in the command register.
Table 5-7 ASSERTION OF P_SERR# FOR DATA PARITY ERRORS
P_SERR#
Transaction Type
Direction
Bus Where Error
Was Detected
Primary / Secondary Parity
Error Response Bits
1 (de-asserted)
Read
Downstream
Primary
x / x
1
Read
Downstream
Secondary
x / x
1
Read
Upstream
Primary
x / x
1
Read
Upstream
Secondary
x / x
1
Posted Write
Downstream
Primary
x / x
02 (asserted)
Posted Write
Downstream
Secondary
1 / 1
03
Posted Write
Upstream
Primary
1 / 1
1
Posted Write
Upstream
Secondary
x / x
1
Delayed Write
Downstream
Primary
x / x
1
Delayed Write
Downstream
Secondary
x / x
1
Delayed Write
Upstream
Primary
x / x
1
Delayed Write
Upstream
Secondary
x / x
Note: x=don’t care
5.4
SYSTEM ERROR (SERR#) REPORTING
PI7C8154A uses the P_SERR# signal to report conditionally a number of system error conditions
in addition to the special case parity error conditions described in Section 5.2.3.
Whenever assertion of P_SERR# is discussed in this document, it is assumed that the following
conditions apply:
For the bridge to assert P_SERR# for any reason, the SERR# enable bit must be set in the
command register.
Whenever the bridge asserts P_SERR#, PI7C8154A must also set the signaled system error bit
in the status register.
In compliance with the PCI-to-PCI Bridge Architecture Specification, the bridge asserts P_SERR#
when it detects the secondary SERR# input, S_SERR#, asserted and the SERR# forward enable bit
is set in the bridge control register. In addition, the bridge also sets the received system error bit in
the secondary status register.
The bridge also conditionally asserts P_SERR# for any of the following reasons:
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