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參數(shù)資料
| 型號(hào)： | PI7C8154ANAE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 58/114頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 48 of 114
DEC 2009 REVISION 1.02
registers correspond to bits [31:20] of the memory address. The lowest 4 bits are hardwired to 1h.
The lowest 20 bits of the prefetchable memory base address are assumed to be 0 0000h, which
results in a natural alignment to a 1MB boundary. The lowest 20 bits of the prefetchable memory
limit address are assumed to be FFFFFh, which results in an alignment to the top of a 1MB block.
Note: The initial state of the prefetchable memory base address register is 0000 0000h. The initial
state of the prefetchable memory limit address register is 000F FFFFh. Note that the initial states of
these registers define a prefetchable memory range at the bottom 1MB block of memory. Write
these registers with their appropriate values before setting either the memory enable bit or the
master enable bit in the command register in configuration space.
To turn off the prefetchable memory address range, write the prefetchable memory base address
register with a value greater than that of the prefetchable memory limit address register. The entire
base value must be greater than the entire limit value, meaning that the upper 32 bits must be
considered. Therefore, to disable the address range, the upper 32 bits registers can both be set to the
same value, while the lower base register is set greater than the lower limit register. Otherwise, the
upper 32-bit base must be greater than the upper 32-bit limit.
3.3.3
PREFETCHABLE MEMORY 64-BIT ADDRESSING REGISTERS
PI7C8154A supports 64-bit memory address decoding for forwarding of dual address memory
transactions. Dual address cycle is used for 64-bit addressing. The first address phase of the dual
address cycle contains the low 32 bits of the address and the second address phase contains the
high 32 bits. The high 32 bits must never be 0 during a dual address cycle.
The prefetchable memory address range is defined by implementing the prefetchable memory base
address upper 32 bits register and the prefetchable memory limit address upper 32 bits register.
The prefetchable address space can be defined as either:
Residing entirely in the first 4GB of memory
Residing entirely above the first 4GB of memory
Crossing the first 4GB memory boundary
If the prefetchable memory space on the secondary bus resides entirely in the first 4GB of memory,
both upper 32 bit register must be set to 0. PI7C8154A then ignores all dual address cycles
initiated on the primary interface and forwards all dual address transactions initiated on the
secondary interface upstream.
If the prefetchable memory space on the secondary bus resides entirely above the first 4GB of
memory, both the prefetchable memory base address upper 32 bit register and the prefetchable
memory limit address upper 32 bit register must be initialized to nonzero values. PI7C8154A
ignores all single address memory transactions initiated on the primary and forwards all single
address memory transactions initiated on the secondary upstream, unless the memory falls within
the memory mapped I/O or VGA memory range. A dual address memory transaction is forwarded
downstream from the primary if it falls within the address range defined by the prefetchable
memory base address, prefetchable memory base address upper 32 bits, prefetchable memory limit
address, and prefetchable memory limit address upper 32 bits. If the dual address cycle initiated on
the secondary falls outside this address range, it is forwarded upstream to the primary. PI7C8154A
does not respond to a dual address cycle initiated on the primary that falls outside this address
range, or to a dual address cycle initiated on the secondary that falls within the address range.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154ANAE-33 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
| PI7C8154BNA | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154BNAE-80 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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