Advance Information Page 90 of 114 DEC 2009 REVISION 1.02 14.1.39 UPSTREAM (S TO P) MEMORY BASE" />
參數(shù)資料
型號(hào): PI7C8154ANAE
廠商: Pericom
文件頁數(shù): 105/114頁
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE ASYNC 304-PBGA
標(biāo)準(zhǔn)包裝: 27
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 304-BBGA
供應(yīng)商設(shè)備封裝: 304-PBGA(31x31)
包裝: 管件
安裝類型: 表面貼裝
PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 90 of 114
DEC 2009 REVISION 1.02
14.1.39
UPSTREAM (S TO P) MEMORY BASE ADDRESS REGISTER – OFFSET
58h
Bit
Function
Type
Description
3:0
64-bit
Addressing
R/O
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 0
15:4
Upstream
Memory Base
R/W
Defines the bottom address of an address range used by the bridge to
determine when to forward upstream memory transactions.
Reset to 0
14.1.40
UPSTREAM (S TO P) MEMORY LIMIT ADDRESS REGISTER – OFFSET
58h
Bit
Function
Type
Description
19:16
64-bit
Addressing
R/O
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 0
31:20
Upstream
Memory Limit
R/W
Defines the top address of an address range used by the bridge to
determine when to forward upstream memory transactions.
Reset to 0
14.1.41
UPSTREAM (S TO P) MEMORY BASE ADDRESS UPPER 32-BIT
REGISTER – OFFSET 5Ch
Bit
Function
Type
Description
31:0
Upstream
Memory Base
Upper 32-bits
R/W
Defines the upper 32-bits of a 64-bit bottom address of an address range
for the bridge to determine when to forward upstream memory read and
write transactions.
Reset to 0
14.1.42
UPSTREAM (S TO P) MEMORY LIMIT ADDRESS UPPER 32-BIT
REGISTER – OFFSET 60h
Bit
Function
Type
Description
31:0
Upstream
Memory Base
Upper 32-bits
R/W
Defines the upper 32-bits of a 64-bit top address of an address range for
the bridge to determine when to forward upstream memory read and write
transactions.
Reset to 0
14.1.43
P_SERR# EVENT DISABLE REGISTER – OFFSET 64h
Bit
Function
Type
Description
0
Reserved
R/O
Returns 0 when read. Reset to 0
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