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參數(shù)資料
| 型號(hào)： | PI7C8154ANAE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 3/114頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 100 of 114
DEC 2009 REVISION 1.02
15
BRIDGE BEHAVIOR
A PCI cycle is initiated by asserting the FRAME# signal. In a bridge, there are a number of
possibilities. Those possibilities are summarized in the table below:
15.1
BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES
Initiator
Target
Response
Master on Primary
Target on Primary
PI7C8154A does not respond. It detects this
situation by decoding the address as well as
monitoring the P_DEVSEL# for other fast and
medium devices on the Primary Port.
Master on Primary
Target on Secondary
PI7C8154A asserts P_DEVSEL#, terminates
the cycle normally if it is able to be posted,
otherwise return with a retry. It then passes the
cycle to the appropriate port. When the cycle is
complete on the target port, it will wait for the
initiator to repeat the same cycle and end with
normal termination.
Master on Primary
Target not on Primary nor
Secondary Port
PI7C8154A does not respond and the cycle will
terminate as master abort.
Master on Secondary
Target on the same
Secondary Port
PI7C8154A does not respond.
Master on Secondary
Target on Primary or the
other Secondary Port
PI7C8154A asserts S_DEVSEL#, terminates
the cycle normally if it is able to be posted,
otherwise returns with a retry. It then passes
the cycle to the appropriate port. When cycle is
complete on the target port, it will wait for the
initiator to repeat the same cycle and end with
normal termination.
Master on Secondary
Target not on Primary nor
the other Secondary Port
PI7C8154A does not respond.
15.2
ABNORMAL TERMINATION (INITIATED BY BRIDGE
MASTER)
15.2.1
MASTER ABORT
Master abort indicates that when PI7C8154A acts as a master and receives no response (i.e., no
target asserts DEVSEL# or S_DEVSEL#) from a target, the bridge deasserts FRAME# and then
de-asserts IRDY#.
15.2.2
PARITY AND ERROR REPORTING
Parity must be checked for all addresses and write data. Parity is defined on the P_PAR, P_PAR64,
S_PAR, and S_PAR64 signals. Parity should be even (i. e. an even number of‘1’s) across AD,
CBE, and PAR. Parity information on PAR is valid the cycle after AD and CBE are valid. For
reads, even parity must be generated using the initiators CBE signals combined with the read data.
Again, the PAR signal corresponds to read data from the previous data phase cycle.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154ANAE-33 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
| PI7C8154BNA | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154BNAE-80 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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