Advance Information Page 82 of 114 DEC 2009 REVISION 1.02 Bit Function Type Description 31 Dete" />
參數(shù)資料
型號: PI7C8154ANAE
廠商: Pericom
文件頁數(shù): 96/114頁
文件大小: 0K
描述: IC PCI-PCI BRIDGE ASYNC 304-PBGA
標準包裝: 27
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 304-BBGA
供應(yīng)商設(shè)備封裝: 304-PBGA(31x31)
包裝: 管件
安裝類型: 表面貼裝
PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 82 of 114
DEC 2009 REVISION 1.02
Bit
Function
Type
Description
31
Detected Parity
Error
R/WC
Set to 1 when address or data parity error is detected on the secondary
interface
Reset to 0
14.1.18
MEMORY BASE REGISTER – OFFSET 20h
Bit
Function
Type
Description
3:0
Reserved
R/O
Lower four bits of register are read only and return 0.
Reset to 0
15:4
Memory Base
Address [15:4]
R/W
Defines the bottom address of an address range for the bridge to
determine when to forward memory transactions from one interface to the
other. The upper 12 bits correspond to address bits [31:20] and are
writable. The lower 20 bits corresponding to address bits [19:0] are
assumed to be 0.
Reset to 0
14.1.19
MEMORY LIMIT REGISTER – OFFSET 20h
Bit
Function
Type
Description
19:16
Reserved
R/O
Lower four bits of register are read only and return 0.
Reset to 0
31:20
Memory Limit
Address [31:20]
R/W
Defines the top address of an address range for the bridge to determine
when to forward memory transactions from one interface to the other.
The upper 12 bits correspond to address bits [31:20] and are writable.
The lower 20 bits corresponding to address bits [19:0] are assumed to be
FFFFFh.
14.1.20
PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h
Bit
Function
Type
Description
3:0
64-bit addressing
R/O
Indicates 64-bit addressing
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 0001
15:4
Prefetchable
Memory Base
Address [31:20]
R/W
Defines the bottom address of an address range for the bridge to
determine when to forward memory read and write transactions from one
interface to the other. The upper 12 bits correspond to address bits
[31:20] and are writable. The lower 20 bits are assumed to be 0.
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