Advance Information Page 96 of 114 DEC 2009 REVISION 1.02 Bit Function Type Description 13 Orde" />
參數(shù)資料
型號: PI7C8154ANAE
廠商: Pericom
文件頁數(shù): 111/114頁
文件大小: 0K
描述: IC PCI-PCI BRIDGE ASYNC 304-PBGA
標準包裝: 27
系列: *
應用: *
接口: *
電源電壓: *
封裝/外殼: 304-BBGA
供應商設備封裝: 304-PBGA(31x31)
包裝: 管件
安裝類型: 表面貼裝
PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 96 of 114
DEC 2009 REVISION 1.02
Bit
Function
Type
Description
13
Ordering Rules
Control 2
R/W
0: Keep the ordering rule requirements between delay read completion
and posted write transactions
1: Disregard the ordering rule requirements between delay read
completion and posted write transactions
Reset to 0
15:14
Reserved
R/W
Reset to 0
14.1.48
SECONDARY MASTER TIMEOUT COUNTER REGISTER – OFFSET
80h
Bit
Function
Type
Description
15:0
Secondary
Master Timeout
R/W
Secondary timeout occurs after 215 PCI clocks.
Reset to 8000h.
14.1.49
PRIMARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 80h
Bit
Function
Type
Description
31:16
Primary Master
Timeout
R/W
Primary timeout occurs after 215 PCI clocks.
Reset to 8000h.
14.1.50
CAPABILITY ID REGISTER – OFFSET B0h
Bit
Function
Type
Description
7:0
Enhanced
Capabilities ID
R/O
Read as 04h to indicate that these are Slot Indentification registers.
14.1.51
NEXT POINTER REGISTER – OFFSET B0h
Bit
Function
Type
Description
15:8
Next Item
Pointer
R/O
Read as E8h. Points to Vital Products Data register.
14.1.52
SLOT NUMBER REGISTER – OFFSET B0h
Bit
Function
Type
Description
20:16
Expansion Slot
Number
R/W
Indicates expansion slot number
Reset to 0
21
First in Chassis
R/W
First in chassis
Reset to 0
23:22
Reserved
R/O
Returns 0 when read. Reset to 0
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