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參數(shù)資料
| 型號： | PI7C8154ANAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 44/114頁 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 35 of 112
DEC 2009 REVISION 1.02
2.9
64-BIT OPERATION
Both the primary and secondary interfaces of the PI7C8154A support 32-bit operation and 64-bit
operation. This chapter describes how to use the 64-bit operations as well as the conditions that go
along with it.
2.9.1
64-BIT AND 32-BIT TRANSACTIONS INITIATED BY PI7C8154A
64-bit transactions are requested by asserting P_REQ64# on the primary and S_REQ64# on the
secondary during the address phase. REQ64# is asserted and deasserted during the same cycles as
FRAME#. Under certain conditions, PI7C8154A does not use the 64-bit extension when initiating
transactions. In this case, REQ64# is not asserted.
If REQ64# is not asserted, the transaction is initiated as a 32-bit transaction when any of the
following conditions are met:
P_REQ64# was not asserted by the primary during reset (64-bit extension not supported on the
primary) for upstream transactions only
PI7C8154A is initiating an I/O transaction
PI7C8154A is initiating a special cycle transaction
PI7C8154A is initiating a configuration transaction
PI7C8154A is initiating a nonprefetchable memory read transaction
The address is not QUADWORD aligned
The address is near the top of a cache line
A single DWORD read transaction is being performed
A single or two-DWORD memory write transaction is being performed
PI7C8154A is resuming memory write transaction after a target disconnect, and ACK64# was
not asserted by the target in the previous transaction – does not apply when the previous target
termination was a target retry
2.9.2
64-BIT TRANSACTIONS – ADDRESS PHASE
When a transaction using the primary bus 64-bit extension is a single address cycle, the upper 32-
bits of the address, AD[63:32], are assumed to be 0 and CBE[7:4] are not defined but driven to
valid logic levels during the address phase.
When a transaction using the primary bus 64-bit extension is a dual address cycle, the upper 32-bit
of the address, AD[63:32], contain the upper 32-bits of the address and CBE[7:4] contain memory
bus command during both address phases. A 64-bit target then has the opportunity to decode the
entire 64-bit address and bus command after the first address phase. A 32-bit target needs both
address phases to decode the full address and bus command.
2.9.3
64-BIT TRANSACTIONS – DATA PHASE
PI7C8154A asserts REQ64# to indicate it is initiating a 64-bit transfer during memory write
transactions. During the data phase, PI7C8154A asserts the following:
The low 32 bits of data on AD[31:0]
The low 4 bits on CBE[3:0]
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154ANAE-33 | 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
| PI7C8154BNA | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAE | 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154BNAE-80 | 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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