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參數(shù)資料
| 型號： | PI7C8154ANAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 52/114頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 42 of 114
DEC 2009 REVISION 1.02
2-9 shows the response to each type of target termination that occurs during a delayed read
transaction.
PI7C8154A repeats a delayed read transaction until one of the following conditions is met:
PI7C8154A completes at least one data transfer.
PI7C8154A receives a master abort.
PI7C8154A receives a target abort.
PI7C8154A makes 224 (default) read attempts resulting in a response of target retry.
Table 2-9 RESPONSE TO DELAYED READ TARGET TERMINATION
Target Termination
Response
Normal
If prefetchable, target disconnect only if initiator requests more data than read
from target. If non-prefetchable, target disconnect on first data phase.
Target Retry
Re-initiate read transaction to target
Target Disconnect
If initiator requests more data than read from target, return target disconnect to
initiator.
Target Abort
Return target abort to initiator. Set received target abort bit in the target
interface status register. Set signaled target abort bit in the initiator interface
status register.
After PI7C8154A makes 224(default) attempts of the same delayed read transaction on the target
bus, PI7C8154A asserts P_SERR# if the primary SERR# enable bit is set (bit 8 of command
register for secondary bus) and the delayed-write-non-delivery bit is not set. The delayed-write-
non-delivery bit is bit 5 of P_SERR# event disable register (offset 64h). PI7C8154A will report
system error. See Section 5.4 for a description of system error conditions.
2.11.4
TARGET TERMINATION INITIATED BY PI7C8154A
PI7C8154A can return a target retry, target disconnect, or target abort to an initiator for reasons
other than detection of that condition at the target interface.
2.11.4.1
TARGET RETRY
PI7C8154A returns a target retry to the initiator when it cannot accept write data or return read data
as a result of internal conditions. PI7C8154A returns a target retry to an initiator when any of the
following conditions is met:
FOR DELAYED WRITE TRANSACTIONS:
The transaction is being entered into the delayed transaction queue.
Transaction has already been entered into delayed transaction queue, but target response has
not yet been received.
Target response has been received but has not progressed to the head of the return queue.
The delayed transaction queue is full, and the transaction cannot be queued.
A transaction with the same address and command has been queued.
A locked sequence is being propagated across PI7C8154A, and the write transaction is not a
locked transaction.
The target bus is locked and the write transaction is a locked transaction.
Use more than 16 clocks to accept this transaction.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154ANAE-33 | 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
| PI7C8154BNA | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAE | 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154BNAE-80 | 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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