- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1961 > PI7C8154ANAE (Pericom)IC PCI-PCI BRIDGE ASYNC 304-PBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | PI7C8154ANAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 20/114頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁
PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 13 of 112
DEC 2009 REVISION 1.02
Name
Pin #
Type
Description
P_IRDY#
AC5
STS
Primary IRDY (Active LOW). Driven by the
initiator of a transaction to indicate its ability to
complete current data phase on the primary side.
Once asserted in a data phase, it is not de-asserted
until the end of the data phase. Before tri-stated, it
is driven to a de-asserted state for one cycle.
P_TRDY#
AB5
STS
Primary TRDY (Active LOW). Driven by the
target of a transaction to indicate its ability to
complete current data phase on the primary side.
Once asserted in a data phase, it is not de-asserted
until the end of the data phase. Before tri-stated,
it is driven to a de-asserted state for one cycle.
P_DEVSEL#
AA6
STS
Primary Device Select (Active LOW). Asserted
by the target indicating that the device is accepting
the transaction. As a master, bridge waits for the
assertion of this signal within 5 cycles of
P_FRAME# assertion; otherwise, terminate with
master abort. Before tri-stated, it is driven to a
de-asserted state for one cycle.
P_STOP#
AC6
STS
Primary STOP (Active LOW). Asserted by the
target indicating that the target is requesting the
initiator to stop the current transaction. Before tri-
stated, it is driven to a de-asserted state for one
cycle.
P_LOCK#
AB6
I
Primary LOCK (Active LOW). Asserted by an
initiator, one clock cycle after the first address phase
of a transaction, attempting to perform an operation
that may take more than one PCI transaction to
complete.
P_IDSEL
Y1
I
Primary ID Select. Used as a chip select line for
Type 0 configuration access to bridge configuration
space.
P_PERR#
AC7
STS
Primary Parity Error (Active LOW). Asserted
when a data parity error is detected for data received
on the primary interface. Before being tri-stated, it
is driven to a de-asserted state for one cycle.
P_SERR#
Y7
OD
Primary System Error (Active LOW). Can be
driven LOW by any device to indicate a system
error condition. Bridge drives this pin on:
Address parity error
Posted write data parity error on target bus
Secondary S_SERR# asserted
Master abort during posted write transaction
Target abort during posted write transaction
Posted write transaction discarded
Delayed write request discarded
Delayed read request discarded
Delayed transaction master timeout
This signal requires an external pull-up resistor for
proper operation.
P_REQ#
U3
TS
Primary Request (Active LOW): This is asserted
by BRIDGE to indicate that it wants to start a
transaction on the primary bus. Bridge de-asserts
this pin for at least 2 PCI clock cycles before
asserting it again.
P_GNT#
R2
I
Primary Grant (Active LOW): When asserted,
PI7C8154A can access the primary bus. During idle
and P_GNT# asserted, bridge will drive P_AD,
P_CBE, and P_PAR to valid logic levels.
P_RESET#
R3
I
Primary RESET (Active LOW): When
P_RESET# is active, all PCI signals should be
asynchronously tri-stated.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8154BNAIE | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| PI7C9X110BNBE | IC PCIE TO PCI REV BRG 160LFBGA |
| PI7C9X130DNDE | IC PCIE-PCIX BRIDGE 1PORT 256BGA |
| PI7C9X20303SLCFDE | IC PCIE PACKET SWITCH 128LQFP |
| PI7C9X20303ULAZPE | IC PCIE PACKET SWITCH 132TQFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154ANAE-33 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
| PI7C8154BNA | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154BNAE-80 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。