參數(shù)資料
型號: CD1283
廠商: Intel Corp.
英文描述: IEEE 1284-Compatible Parallel Interface
中文描述: 符合IEEE 1284兼容并行接口
文件頁數(shù): 89/94頁
文件大?。?/td> 1237K
代理商: CD1283
IEEE 1284-Compatible Parallel Interface
CD1283
Datasheet
89
Figure 29. Synchronous DMA Write Cycle Timing
(Two Back-to-Back 3-Cycle DMA Writes)
Figure 30. Synchronous DMA Read Cycle Timing
(Two Back-to-Back 3-Cycle DMA Reads)
DB[15:0]
DMAACK*
CLK
NOTE:
The data is sampled on the second rising edge of CLK following the assertion of DMAACK*, as long as
setup time (t
) is met. If DMAACK* is held active for more than 2.5 CLK cycles then the next DMA
cycle is simply delayed, but the data is still sampled on the second rising CLK edge following the
assertion of DMAACK*.
t
16
VALID
DMAREQ*
t
18
VALID
C
C1
C2
C3
C1
C2
C3
C
DATA SAMPLED
HERE
t
15
t
25
t
17
t
22
t
22
t
17
DATA SAMPLED
HERE
SEE NOTE
SEE NOTE
DB[15:0]
DMAACK*
CLK
NOTE:
The data is sampled on the second rising edge of CLK following the assertion of DMAACK*, as long as
setup time (t
) is met. If DMAACK* is held active for more than 2.5 CLK cycles then the next DMA cycle
is simply delayed, but the data is still sampled on the second rising CLK edge following the assertion of
DMAACK*.
VALID
DMAREQ*
t
18
VALID
C
C1
C2
C3
C1
C2
C3
C
t
15
SEE NOTE
SEE NOTE
t
25
t
18
t
24
t
16
t
23
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