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參數(shù)資料
| 型號： | CD1283 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface |
| 中文描述： | 符合IEEE 1284兼容并行接口 |
| 文件頁數(shù)： | 77/94頁 |
| 文件大?。?/td> | 1237K |
| 代理商： | CD1283 |
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IEEE 1284-Compatible Parallel Interface
—
CD1283
Datasheet
77
The signals specific to the parallel port meet all requirements of the IEEE STD 1284 specification,
except for input signal protection (
2.0 to
+
7.0 V); external circuitry is required to meet this
specification.
Note:
While the CD1283 is a highly dependable device, there are a few guidelines to ensure that the
maximum possible level of overall system reliability is achieved. First, design the PC board to
provide maximum isolation of noise. A four-layer board is preferable, but a two-layer board will
work if proper power and ground distribution is implemented. In either case, decoupling capacitors
mounted close to the CD1283 are strongly recommended. Noise typically occurs when either the
CD1283 data bus drivers come out of tristate to drive the bus during a read, or when an external bus
buffer turns on during a write cycle. This noise, a rapid rate-of-change of supply current, causes
‘
ground bounce
’
in the power-distribution traces. This ground bounce, a rise in the voltage of the
ground pins, effectively raises the input logic thresholds of all devices in the vicinity, resulting in
the possibility of a
‘
1
’
being interpreted as a
‘
0
’
.
To reduce the possibility of ground-bounce affecting the operation of the CD1283, Intel has
specified the input-high voltage (V
IH
) of the CLK and RESET* pins at 2.7 V, instead of the TTL-
standard 2.0 V. This eliminates any sensitivity to ground bounce, even in extremely noisy systems.
Although 2.7 V is higher than the industry-standard 2.4-V output (V
OH
) specified for TTL, there
are several simple ways to meet this specification:
1. Use any of the available advanced-CMOS logic families (FACT, ACL, and so on). These
CMOS output buffers will pull-up close to V
CC
when not heavily loaded. In addition, AS and
ALS TTL can be used if the output of the TTL device is only driving one or two CMOS loads.
2. As noted in the Texas Instruments
ALS/AS Logic Data Book
(1986
—
pages 4-18 and 4-19),
the V
OH
output of these families exceeds 3.0 V at low-current loading. Other manufacturers
publish similar data. Intel recommends the use of one of these two options for the CLK input
to ensure fast, clean edges.
Note that RESET* can, if desired, be pulled up passively with
≤
1-k
resistor.
I
LL
Data bus tristate leakage current
10
10
10
μ
A
μ
A
0
<
V
OUT
<
V
CC
0
<
V
OUT
<
V
CC
CLK
=
25 MHz
I
OC
Open-drain output leakage current
10
I
CC
Power supply current
50
mA
C
IN
Input capacitance
10
pF
C
OUT
Output capacitance
10
pF
NOTES:
1. V
IH
is 2.7 V minimum on RESET* and CLK.
2. V
for open-drain signals is 0.5 V @ 8 mA sinking because these signals can be wire-OR
’
ed in some systems and can have
multiple pull-up resistors that increase the load on the output.
Symmetrical input/output drive:
±
14 mA
Controlled voltage slew rate: 0.4 V/
μ
s
Input hysteresis: 0.8 V
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