參數(shù)資料
型號(hào)： CD1283
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface
中文描述： 符合IEEE 1284兼容并行接口
文件頁(yè)數(shù)： 6/94頁(yè)
文件大?。?/td> 1237K
代理商： CD1283
CD1283
—
IEEE 1284-Compatible Parallel Interface
6
Datasheet
Figures
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Functional Block Diagram ...................................................................................10
Functional Block Diagram ...................................................................................23
Internal Address Generation ...............................................................................23
CD1283 Daisy-Chain Configuration....................................................................26
Interrupt Generation Logic ..................................................................................28
Control Signal Generation...................................................................................31
FIFO Data Path Functional Diagram
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Receive..................................................37
FIFO Data Path Functional Diagram: Transmit...................................................38
Supported Compatibility Mode Timing ................................................................40
Cable Connection................................................................................................43
External Buffer Control........................................................................................44
Sample System Block Diagram...........................................................................44
Intel
80x86 Family Interface ...............................................................................45
Motorola
68020 Interface ...................................................................................46
Flow Diagram of the CD1283 Master Initialization Sequence.............................48
Polling Flow Chart...............................................................................................51
Reset Timing.......................................................................................................79
Clock Timing .......................................................................................................80
Asynchronous Read Cycle Timing......................................................................80
Asynchronous Write Cycle Timing ......................................................................81
Asynchronous Service Acknowledge Cycle Timing ............................................82
Asynchronous DMA Read Cycle Timing.............................................................83
Asynchronous DMA Read Cycle Timing (Two Back-to-Back DMA Reads)........83
Asynchronous DMA Write Cycle Timing .............................................................84
Asynchronous DMA Write Cycle Timing .............................................................84
Synchronous Read Cycle Timing........................................................................86
Synchronous Write Cycle Timing........................................................................87
Synchronous Service Acknowledge Cycle Timing..............................................88
Synchronous DMA Write Cycle Timing
(Two Back-to-Back 3-Cycle DMA Writes) ...........................................................89
Synchronous DMA Read Cycle Timing
(Two Back-to-Back 3-Cycle DMA Reads)...........................................................89
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Tables
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Global Registers..................................................................................................19
Virtual Registers..................................................................................................20
Parallel Pipeline Registers..................................................................................20
Parallel Port Registers ........................................................................................20
Special Register..................................................................................................21
LIVR[2:0] Encoding.............................................................................................31
System Clock Setup............................................................................................42
Hexadecimal
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Character..................................................................................51
Decimal
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Character..........................................................................................52
PIVR[2:0] Encoding.............................................................................................56
SPR Binary Values to Set 500-ns Pulse Widths.................................................74
Asynchronous Timing Reference Parameters ....................................................78
Synchronous Timing Reference Parameters......................................................85
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參數(shù)描述
CD1284 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
CD-12AFFM-QL8D01 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10
CD-12AFFM-QR8D01 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10
CD-12AMMM-QL8D01 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10
CD-12BFFA-LL7001 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10
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