參數(shù)資料
型號(hào)： CD1283
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface
中文描述： 符合IEEE 1284兼容并行接口
文件頁(yè)數(shù)： 4/94頁(yè)
文件大?。?/td> 1237K
代理商： CD1283
CD1283 —
IEEE 1284-Compatible Parallel Interface
4
Datasheet
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
Protocol Timing ...................................................................................................41
General-Purpose I/O Port ...................................................................................42
Parallel Port Interface..........................................................................................42
Hardware Configurations ....................................................................................44
5.10.1 Interfacing to an Intel
Microprocessor-Based System...........................45
5.10.2 Interfacing to a Motorola
Microprocessor-Based System......................46
Programming
.............................................................................................................47
6.1
Overview .............................................................................................................47
6.2
Initialization .........................................................................................................47
6.2.1
Device Reset..........................................................................................47
6.2.2
Service Acknowledge Handling..............................................................49
6.3
ASCII Code Tables .............................................................................................51
Detailed Register Descriptions
...........................................................................53
7.1
Global Registers..................................................................................................53
7.1.1
Access Enable Register.........................................................................53
7.1.2
Global Firmware Revision Code Register..............................................53
7.1.3
General-Purpose I/O Direction Register.................................................54
7.1.4
General-Purpose I/O Register................................................................54
7.1.5
Parallel Interrupt Register ......................................................................54
7.1.6
Prescaler Period Register ......................................................................55
7.1.7
Service Request Register ......................................................................55
7.2
Virtual Registers..................................................................................................56
7.2.1
End-of-Service Request Register...........................................................56
7.2.2
Parallel Interrupt Vector Register...........................................................56
7.3
Parallel Pipeline Registers..................................................................................57
7.3.1
Data Error Register ................................................................................57
7.3.2
DMA Buffer Data Register......................................................................58
7.3.3
Holding Register Status Register...........................................................58
7.3.4
Host Timeout Value Register .................................................................59
7.3.5
Local Interrupt Vector Register ..............................................................60
7.3.6
Parallel Auxiliary Control Register..........................................................61
7.3.7
Parallel Channel Reset Register............................................................61
7.3.8
Parallel FIFO Control Register...............................................................62
7.3.9
Parallel FIFO Empty Pointer Register....................................................63
7.3.10 Parallel FIFO Fill Pointer Register..........................................................63
7.3.11 Parallel FIFO Holding Registers.............................................................63
7.3.12 Parallel FIFO Quantity Register .............................................................64
7.3.13 Parallel FIFO Status Register.................................................................64
7.3.14 Parallel FIFO Threshold Register...........................................................65
7.3.15 Run-Length Count Register ...................................................................66
7.3.16 Stale Data Timer Count Register ...........................................................66
7.3.17 Stale Data Timer Period Register...........................................................67
7.4
Parallel Port Registers ........................................................................................67
Compatibility Mode.................................................................................40
Reverse-Nibble and Reverse-Byte Modes.............................................40
ID Request .............................................................................................41
ECP Mode..............................................................................................41
EPP Mode..............................................................................................41
5.7
5.8
5.9
5.10
6.0
7.0
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