參數(shù)資料
型號(hào)： CD1283
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface
中文描述： 符合IEEE 1284兼容并行接口
文件頁(yè)數(shù)： 84/94頁(yè)
文件大?。?/td> 1237K
代理商： CD1283
CD1283
—
IEEE 1284-Compatible Parallel Interface
84
Datasheet
8.3.2
Synchronous Timing
Use the following table as a reference to timing parameters of figures in this section.
Figure 24. Asynchronous DMA Write Cycle Timing
Figure 25. Asynchronous DMA Write Cycle Timing
t
21
t
24
t
19
CLK
DMAACK*
DB[15:0]
MAY CHANGE
VALID
DMAREQ*
NOTE:
This
Figure 24
is still valid, however,
Figure 25
illustrates a more robust timing.
DB[15:0]
DMAACK*
CLK
NOTE:
The data is sampled on the third rising edge of CLK following the assertion of DMAACK*. If DMAACK* is held
active for more than three CLK cycles then the next DMA write cycle will simply be delayed, but the data will
still be sampled on the third rising CLK edge following the assertion of DMAACK*. If DMAACK* is active for
<
3
CLKs, the n the data is still sampled on the third rising CLK edge following the assertion of DMAACK*
(provided that DMAACK* is active long enough for the device to lastch it. Due to this somewhat synchronous
behavior, care must be taken to guarantee that the data is valid at this CLK edge. Do not assume that the data
will be sampled on the deassertion of DMAACK*.
t
32
t
29
VALID
DMAREQ*
t
28
VALID
t
31
t
30
t
30
t
32
t
31
DMAACK* SYNCHRONIZED
HERE
DMAACK* SYNCHRONIZED
HERE
DATA SAMPLED
HERE
DATA SAMPLED
HERE
DMAACK* LATCHED
HERE
SEE NOTE
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