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參數(shù)資料
| 型號(hào)： | CD1283 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface |
| 中文描述： | 符合IEEE 1284兼容并行接口 |
| 文件頁數(shù)： | 22/94頁 |
| 文件大?。?/td> | 1237K |
| 代理商： | CD1283 |
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CD1283
—
IEEE 1284-Compatible Parallel Interface
22
Datasheet
5.0
Functional Description
5.1
Device Architecture
The CD1283 consists of dedicated logic tailored to the function of sending and receiving parallel
data. The device implements an IEEE 1284-compliant parallel port with a specialized data pipeline
designed for high-speed transfers.
To maintain binary compatibility with the CD1284, much of the architectural layout has been
duplicated. Therefore, access to the register set of the parallel channel is only possible after loading
the AER with the CD1284 occupied parallel port address
—
namely channel 0. For all channel-
specific accesses, the CPU first loads the AER with a pointer to channel 0. Thereafter, all read and
write operations occur through the parallel channel.
The parallel channel is comprised of a FIFO and DMA data interface, as well as a high-speed state
machine to manage all modes defined in the IEEE Std 1284-1994 specification,
Standard Signaling
Method for a Bidirectional Parallel Peripheral Interface for Personal Computers
. The parallel port
performs the slave or peripheral function of the IEEE Std 1284 interface, and can accept
negotiations into any or all of the IEEE defined modes.
5.2
CPU Interface
The CPU interface is comprised of a 7-bit address bus, 8-bit bidirectional data bus, 16-bit DMA
port, and control inputs to identify the type of I/O cycle occurring. The signaling and basic timing
match that of the Motorola
68000 family. With the addition of minimal glue logic, the interface
will work with nearly any CPU. A special input is provided to swap the bytes on the data bus to
reduce the necessary logic needed with Intel
-style CPUs.
The interface is completely compatible with the CD1284. Therefore, a CD1283 can be inserted into
a system in instead of a CD1284 and the parallel port operates without any modifications to the
CPU interface, parallel port hardware or software.
In most cases, when the CPU reads or writes an internal CD1283 location, it accesses a location in
a RAM array to serve as a bank of registers. However, some locations are mapped to actual
hardware resources. For example, when a hard output signal is required (such as a service-request
output in the SVRR) or a read of the actual state of an input is necessary (such as a parallel port
handshake signal in the IVR).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD1284 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports |
| CD-12AFFM-QL8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10 |
| CD-12AFFM-QR8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10 |
| CD-12AMMM-QL8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10 |
| CD-12BFFA-LL7001 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10 |
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