參數(shù)資料
型號(hào)： CD1283
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface
中文描述： 符合IEEE 1284兼容并行接口
文件頁(yè)數(shù)： 34/94頁(yè)
文件大?。?/td> 1237K
代理商： CD1283
CD1283
—
IEEE 1284-Compatible Parallel Interface
34
Datasheet
In the receive direction, the DMA request is removed when there are not at least two more bytes
available to transfer or a tagged byte has moved into the data pipeline. In the latter case, an interrupt
is generated to the CPU (IntEn must be true) to remove the tagged data from the pipeline.
The quantity of data transferred within a single DMA request can significantly exceed the capacity
of the FIFO if RLEen is set, the parallel port is in ECP mode, and compressed data is being
transferred. This is because the FIFO always stores the data in compressed form. Since other modes
do not support RLE compression, the CPU should only set RLEen when the parallel port interface
is in ECP mode.
5.4.3
Parallel Port FIFO
The CD1283 has a dedicated 64-byte FIFO with counters to maintain the fill/empty pointer
addresses, logic to manage data transfers, automatic DMA handshake, and status interrupts to the
CPU. A simple register interface provides control over setting the direction of the pipeline,
initializing/resetting the DMA pointers, setting the DMA threshold, and so on. The FIFO
management logic responds to data-transfer requests from the dedicated IEEE 1284 parallel port
state machine.
Byte-alignment issues on transfers to/from the FIFO are avoided by having the FIFO byte-oriented
with 2-byte word packing/unpacking occurring between the DMABUF register and PFHR1 and
PFHR2. The order of byte transfers to/from the DMA buffer is controlled by the BYTESWAP
input. If BYTESWAP is high, the upper byte (bits 15:8) transfers first. If BYTESWAP is low, the
lower byte (bits 7:0) transfers first.
Data transfers to/from the CPU are initiated by a DMA request whenever the quantity of data or
space in the FIFO equals or exceeds the threshold value stored in the PFTR. The DMA request is
deasserted during the DMA cycle determined by the logic to be the last because of filling/emptying
the FIFO or the presence of tagged data in the receive pipeline.
5.4.4
Receive Direction
In the receive direction (DMAdir
=
0), the first two bytes of data placed into the FIFO by the
parallel port are immediately moved into the data pipeline, PFHR1 and PFHR2 (
Figure 7 on
page 37
). This is done in part to make the tagged status of the data visible to the pipeline control
logic. If RLEen is
‘
0
’
, any tagged data from the FIFO must move through the pipeline. However,
tagged data cannot be transferred to the CPU by a DMA transfer from the DMABUF register.
Therefore, the presence of tagged data in the pipeline causes an interrupt to the CPU. The CPU
must then examine the HRSR to determine the pipeline status.
If there is tagged data in one of the holding registers, the CPU must read that register to empty it
and clear the tag. If more data is available in the FIFO, data immediately moves forward to fill the
pipeline. If the FIFO is empty, the pipeline does not move so, if the CPU emptied PFHR2 and
PFHR1 is full, the data in PFHR1 moves forward to PFHR2 only if the FIFO is
not
empty.
The pipeline logic keeps the pipeline full in the receive direction. The value in the threshold
register is tested against the quantity of data in the FIFO. Therefore, a number of characters equal
to the PFTR-threshold value plus two must arrive before a DMA request is made to the CPU to
remove the data.
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