參數(shù)資料
型號(hào)： CD1283
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface
中文描述： 符合IEEE 1284兼容并行接口
文件頁(yè)數(shù)： 37/94頁(yè)
文件大小： 1237K
代理商： CD1283
IEEE 1284-Compatible Parallel Interface
—
CD1283
Datasheet
37
5.5.2
Signal Names
The IEEE-1284 specification uses different names for the nine control signals, depending on the
current mode of operation (
Table 6 on page 31
). The CD1283 uses fixed names for each of the pins.
The names were selected to represent the most commonly used names amongst the various
protocols. The CD1283 device operates as a slave only. There are four input-control signals driven
by the master-side device, and five output-control signals driven by the slave-side device. The
Parallel Data bus (PD[7:0]) is bidirectional.
5.5.3
State Machine
The parallel port is controlled by a large synchronous state machine. The state machine is based on
the IEEE Std 1284-1994 and conforms to all the functional modes (except extensibility link
options, which are not currently defined, as of the print date of this document).
5.5.4
Configuration
At power-up, the interface begins in Compatibility mode (Centronics mode) ready to accept data
from the master. Only the ETxfr bit (PCR[5]) is required to allow transfers in Compatibility mode.
PCR[7:5] enable transfers, negotiations, and Manual mode.
5.5.5
Interrupts
Interrupts are enabled in the PCIER and interrupt status can be read in the PCISR. These two
registers have the same format.
Figure 7. FIFO Data Path Functional Diagram – Receive
D
D
P
P
FIFO (64 BYTES)
TAG (64 BITS)
DB[15:8]
DB[7:0]
PFSR
TAG BIT
(RECEIVE)
M
M
P
STATUS
TAG
TAG
STATUS
NOTE:
Data does not move from the
FIFO to PFHR1 if the OneChar
status bit is true (
Section 5.4.6
on page 35
).
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