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參數(shù)資料
| 型號： | CD1283 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface |
| 中文描述： | 符合IEEE 1284兼容并行接口 |
| 文件頁數(shù)： | 60/94頁 |
| 文件大?。?/td> | 1237K |
| 代理商： | CD1283 |
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CD1283
—
IEEE 1284-Compatible Parallel Interface
60
Datasheet
The computed value is rounded up to the next largest whole hex value, in this case
‘
0x3000
’
. Load
HTVR with the most-significant 8 bits of this value, left-shifted two places since HTVR is a 14-bit
counter. This results in a value of
‘
0xC0
’
. For 20 MHz, the value is computed to be
‘
0x9C
’
and for
16 MHz, the value is
‘
0x7C
’
; values for other clocks can be easily computed in the same manner.
At reset, the HTVR defaults to a value of
‘
0xFF
’
; this prevents the extremely short Timeouts that
occur if the register is cleared at device reset and not initialized.
A timeout causes a negotiation status change interrupt. This status is displayed as 0x22 in the
Negotiation Status Register (Host Timeout (bit 5), and the code for return to Compatibility mode
(0010) in the result code field). When Compatibility mode is reentered, the port control state
machine waits in a locked state until signals on the parallel port return to normal Compatibility
mode conditions.
For debug purposes, disable the host Timeout timer by setting PCR bits 2 and 3 (Host Timer Test
[1:0]). In this case, no Timeouts occur and the link can hang indefinitely while waiting for a host-
generated event.
7.3.5
Local Interrupt Vector Register
This read/write register can be initialized to any desired value and, when read in the normal context
(that is, not a service acknowledge context), the same value is returned. The upper 5 bits are copied
into the appropriate vector register, PIVR when the SVCACKP* signal is activated
and
SVCREQP* is active. During this hardware-activated service acknowledge read cycle, the PIVR is
driven onto the data bus, DB[7:0]. Bits 7:3 come from LIVR and bits 2:0 are supplied by the
CD1283 (
Section 7.2.2 on page 56
for details). This value can be used as a vector into the
appropriate service routine (typical in Motorola-type systems) or as a device identifier for systems
with multiple, daisy-chained CD1283s. Bits 2:0 are ignored. Initialization of this register is only
necessary if vectored interrupts are used.
25
MHz
2048
------------------
12207
10
2
FAF
16
=
=
Register Name: LIVR
Register Description: Local Interrupt Vector
Access: R/W
8-Bit Hex Address: 18
Default Value: 00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
User-Defined Bits
X
X
X
Bit
Description
7:3
User-Defined Interrupt Vector:
Host software can use these five bits for any purpose appropriate to the
application. In some cases, these bits might define the rest of a complete interrupt response vector (Motorola-
type systems). In the case of daisy-chain systems made up of multiple CD1283s, these bits are used to define
the device number in the chain.
2:0
These bits are
‘
don
’
t cares
’
.
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