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參數(shù)資料
| 型號： | CD1283 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface |
| 中文描述： | 符合IEEE 1284兼容并行接口 |
| 文件頁數(shù)： | 17/94頁 |
| 文件大?。?/td> | 1237K |
| 代理商： | CD1283 |
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IEEE 1284-Compatible Parallel Interface
—
CD1283
Datasheet
17
SVCREQP*
68
OD
ACTIVE-LOW SERVICE REQUEST PARALLEL:
This is an open-drain output and
must be tied to external V
through a pull-up resistor. Note that this output is only acti-
vated by certain conditions on the parallel port (such as, negotiation changes, direction
changes, etc.). SVCREQP* is not activated by FIFO threshold, or FIFO full/empty con-
ditions (refer to
Chapter 5.0
for information on how to use DMAREQ* to implement a
fully interrupt-driven system).
SVCACKP*
69
I
ACTIVE-LOW SERVICE ACKNOWLEDGE PARALLEL:
This input must not be driven
active except in response to a parallel service request presented by the device.
DGRANT*
70
I
ACTIVE-LOW DAISY GRANT:
This input is driven active during service acknowledge
cycles to enable the daisy-chain function. This input, when qualified with DS* and a
valid service acknowledge (SVCACKP*), activates the service acknowledge cycle.
DPASS*
71
O
ACTIVE-LOW DAISY PASS:
This output is driven active during service acknowledge
cycles to enable the next device in the daisy-chain. It is driven active when no valid
service request exists and the service acknowledge input is active. In multiple CD1283
designs, this signal is normally connected to the DGRANT* input of the next device in
the chain.
PD[7:0]
41
–
48
I/O
PARALLEL PORT DATA LINES [7:0]:
Bidirectional, depending on the protocol being
used, these signals are used to transfer data over the interface between the master
and slave.
GP[7:0]
53
–
60
I/O
GENERAL-PURPOSE I/O [7:0]:
General-purpose input/output port data lines. These
signals are individually direction-programmable, acting as inputs or outputs. The
direction of each signal is controlled by the corresponding bit in the GPDIR register.
Control/status of the actual signals is provided through the GPIO register.
A_1284
31
I
ACTIVE-HIGH 1284 ACTIVE INPUT:
(SLCTIN* in Compatibility mode).
nInit
34
I
ACTIVE-LOW INIT SIGNAL:
(INIT* in Compatibility mode).
HstBsy
32
I
ACTIVE-HIGH HOST BUSY SIGNAL:
(AUTOFD* in Compatibility mode).
HstClk
33
I
ACTIVE-LOW HOST CLOCK SIGNAL:
(STROBE* in Compatibility mode).
NOTE:
The above four parallel handshake signals are driven by the master in an IEEE Std 1284 interface, and as such are
inputs to the CD1283. Their functions depend on the transfer protocol selected. Refer to the IEEE Std 1284-1994
document for protocol functions. (See
Chapter 10.0
for ordering information.)
PerClk
37
O
ACTIVE-LOW PERIPHERAL CLOCK:
(ACK* in Compatibility mode)
PerBsy
36
O
ACTIVE-HIGH PERIPHERAL BUSY:
(BUSY in Compatibility mode)
AkDaRq
35
O
ACKNOWLEDGE DATA REQUEST:
(PERROR* in Compatibility mode)
Xflag
39
O
EXTENSIBILITY FLAG:
(SELECT in Compatibility mode)
nDatAv
38
O
ACTIVE-LOW DATA AVAILABLE SIGNAL:
(FAULT* in Compatibility mode)
Symbol
Pin No.
Type
Description
(Sheet 2 of 3)
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相關(guān)代理商/技術(shù)參數(shù) |
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| CD1284 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports |
| CD-12AFFM-QL8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標準包裝:10 |
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