參數(shù)資料
型號(hào): CD1283
廠商: Intel Corp.
英文描述: IEEE 1284-Compatible Parallel Interface
中文描述: 符合IEEE 1284兼容并行接口
文件頁(yè)數(shù): 78/94頁(yè)
文件大?。?/td> 1237K
代理商: CD1283
CD1283
IEEE 1284-Compatible Parallel Interface
78
Datasheet
8.3
AC Characteristics
8.3.1
Asynchronous Timing
Refer to
Figure 17
through
Figure 25
for the reference numbers in
Table 12
.
(@ V
CC
= 5 V
±
5%, T
A
= 0
°
C to 70
°
C)
Table 12. Asynchronous Timing Reference Parameters
(Sheet 1 of 2)
Timing
No.
Figure
Parameter
MIN
MAX
Unit
t
1
17
RESET*
1
low pulse width
10
T
CLK
t
2
19
Address setup time to CS* or DS*
10
ns
t
3
19
R/W* setup time to CS* or DS*
10
ns
t
4
19
Address hold time after CS*
0
ns
t
5
19
R/W* hold time after CS*
0
ns
t
6
19
DTACK* low to read data valid
10
ns
t
7
19
DTACK* low from CS* or DS
2
2 T
CLK
4 T
CLK
+
30
ns
t
8
19
Data bus tristate after CS* or DS* high
0
30
ns
t
9
19
CS* or DGRANT* high from DTACK* low
0
ns
t
10
19
DTACK* inactive from CS* or DGRANT* and DS* high
40
ns
t
11
19
DS* high pulse width
10
ns
t
12
20
Write data valid from CS* and DS* low
1T
CLK
ns
t
13
20
Write data hold time after DS* high
0
ns
t
14
18
Clock period (T
CLK
)
1, 3
Clock low time
1
40.0
1000
ns
t
15
18
0.3 T
CLK
0.7 T
CLK
ns
t
16
18
Clock high time
1
0.3 T
CLK
0.7 T
CLK
ns
t
17
21
Propagation delay, DGRANT* and DS* to DPASS*
35
ns
t
18
21
Setup time, SVCACK* to DS* and DGRANT*
10
ns
t
19
22
Setup time, DMAACK* to rising edge of CLK
10
ns
t
20
22
Hold time, read data after rising edge of CLK
10
30
ns
t
21
24
Setup time, write data to rising edge of CLK
0
ns
t
22
19
DTACK* active pull-up time
4
ns
t
23
22
Data valid after falling edge of CLK (DMA read)
25
ns
t
24
22
24
Hold time, DMAREQ* after DMAACK* falling edge,
last DMA cycle
10
1 CLK
+
15
ns
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