參數(shù)資料
型號(hào)： CD1283
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface
中文描述： 符合IEEE 1284兼容并行接口
文件頁(yè)數(shù)： 68/94頁(yè)
文件大?。?/td> 1237K
代理商： CD1283
CD1283
—
IEEE 1284-Compatible Parallel Interface
68
Datasheet
7.4.3
Manual Data Register
This read/write register can read the state of the PD[7:0] signals in any mode. If the ManMd bit
(PCR[7])is set along with the MMDir and ManOE bits (PCR[1:0]), then the value written into this
register is driven onto the PD[7:0] signals.
7.4.4
Negotiation Enable Register
Each bit set along with E1284 (PCR[6]) allows the CD1284 to engage in IEEE STD 1284
negotiations and move into the corresponding protocol. It is assumed that the peripheral host
software responds to a request for slave ID and is able to send an ID string in any protocol that it
supports. In response to an ID request, the CD1284 does not provide a method of storing and
automatically sending an ID string. Note that the EPP protocol does not have provision for slave ID
requests.
Bit
Description
7:4
These read-only bits are always
‘
0
’
.
3
A1284
2
nInit:
(active-low Init input)
1
HstBsy:
(Host Busy)
0
HstClk:
(Host Clock)
Register Name: MDR
Register Description: Manual Data
Access: R/W
8-Bit Hex Address: 21
Default Value: 00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
8-Bit Binary Data
Register Name: NER
Register Description: Negotiation Enable
Access: R/W
8-Bit Hex Address: 28
Default Value: 00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
RID
0
EPP
RLE
ECP
RVB
RVN
Bit
Description
7
Reserved:
This read-only bit is always
‘
0
’
.
6
Request Slave ID
5
Reserved:
This bit must always be
‘
0
’
.
4
EPP Mode Enable
3
Run Length Encoding in ECP Mode Enable
2
ECP Mode Enable
1
Reverse Byte Mode Enable
0
Reverse Nibble Mode Enable
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