參數(shù)資料
型號(hào)： CD1283
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface
中文描述： 符合IEEE 1284兼容并行接口
文件頁(yè)數(shù)： 18/94頁(yè)
文件大?。?/td> 1237K
代理商： CD1283
CD1283
—
IEEE 1284-Compatible Parallel Interface
18
Datasheet
NOTE:
The above five parallel handshake signals are driven by the slave in an IEEE Std 1284 interface, and as such are
outputs from the CD1283. Their functions depend on the transfer protocol selected. Refer to the IEEE Std 1284-1994
document for protocol functions. (See
Section 5.4.1 on page 33
for ordering information.)
EBDIR
49
O
EXTERNAL BUFFER DIRECTION:
This signal is controlled by the internal parallel
port control state machine and can be used to control the direction of an external buffer
connected to the Parallel Port data bus. An external buffer might be desirable in
applications that require higher drive capacity than that provided by the CD1283.
EBDIR can be used in conjunction with PDBEN to control this buffer. EBDIR is a logic
‘
0
’
when the parallel data bus is in an output mode, and a logic
‘
1
’
when in an input
mode. It can be connected directly to the direction control input of a 74245-type device.
PDBEN
51
O
PARALLEL DATA BUS ENABLE:
This signal can control a buffer on the Parallel Port
data lines in applications requiring more signal-drive capability than provided by the
CD1283. PDBEN is controlled by the internal Parallel Port control state machine.
When low, the parallel port data bus is not driving; when high, the port is in output
mode and is actively driving. PDBEN will toggle between the on and off states during
output modes and is only active (high) while the data bus pins are in the active driving
state. PDBEN can be logically connected to the enable control of 74245 (or equivalent)
bidirectional buffers (see
Section 5.9
and
Figure 11
).
Symbol
Pin No.
Type
Description
(Sheet 3 of 3)
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