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參數(shù)資料
| 型號(hào)： | CD1283 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface |
| 中文描述： | 符合IEEE 1284兼容并行接口 |
| 文件頁數(shù)： | 83/94頁 |
| 文件大小： | 1237K |
| 代理商： | CD1283 |
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IEEE 1284-Compatible Parallel Interface
—
CD1283
Datasheet
83
Figure 22. Asynchronous DMA Read Cycle Timing
Figure 23. Asynchronous DMA Read Cycle Timing (Two Back-to-Back DMA Reads)
t
20
t
23
t
24
t
19
DB[15:0]
DMAACK*
CLK
‘
a
’
‘
b
’
NOTES:
1. The DMA handshake operates in asynchronous mode only if the AsyncDMA bit is set in PACR.
2. If DMAACK* is released after point
‘
a,
’
but before point
‘
b
’
(two rising CLK edges after the falling edge of DMAACK*), DB[15:0]
is released at t
following the rising edge of CLK. If DMAACK* is held past this edge, it controls the release of DB[15:0]; the
data bus remains active until DMAACK* becomes inactive (point
‘
c
’
).
3. This
Figure 22
is still valid, however,
Figure 23
illustrates a more robust timing.
‘
c
’
MAY CHANGE
VALID
DMAREQ*
DB[15:0]
DMAACK*
CLK
NOTE:
The falling edge of DMAACK* is synchronized internally with the rising edge of the clock when
asynchronous timing is selected by PACR[1]. The data valid time can vary by as much as one full CLK
cycle depending on when DMAACK* falling edge occurs in relation to the CLK rising edge. The minimum
DMAACK* active time must be met to ensure that the data has become valid before the rising edge of
DMAACK*. The DMAACK* can be extended to any length, which extends the data valid hold time
accordingly. If t
is not met and DMAACK* is deasserted in less than t
(MIN), then the data bus
tristates t
27
after the third rising clock edge following the assertion of DMAACK*.
t
27
t
29
VALID
DMAREQ*
SEE NOTE
SEE NOTE
t
28
t
25
VALID
t
26
DMAACK* SYNCHRONIZED
HERE
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