- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379802 > CD1283 (Intel Corp.) IEEE 1284-Compatible Parallel Interface PDF資料下載
參數(shù)資料
| 型號： | CD1283 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface |
| 中文描述： | 符合IEEE 1284兼容并行接口 |
| 文件頁數(shù)： | 79/94頁 |
| 文件大?。?/td> | 1237K |
| 代理商： | CD1283 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁當(dāng)前第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁
IEEE 1284-Compatible Parallel Interface
—
CD1283
Datasheet
79
Note:
For synchronous systems, it is necessary to determine the clock cycle number so that interface
circuitry can stay in lock-step with the device. CLK numbers can be determined if RESET* is
released within the range t
a
–
t
b
; t
a
is defined as 10 ns minimum, after the rising edge of the clock; t
b
is defined as 5 ns minimum, before the next rising edge of the clock. If these conditions are met, the
cycle starting after the second rising edge will be C1. See the synchronous timing diagrams for
additional information. Clock numbers are not important in asynchronous systems.
The following timing numbers are for the back-to-back asynchronous DMA timing diagrams.
t
25
23
Hold time, DMAACK* active (DMA read/write)
3 CLK
t
26
23
Delay, data valid after falling edge DMAACK* (DMA read)
0.5 CLK
+
20
1.5 CLK
+
25
ns
t
27
23
Hold time, data valid after rising edge DMAACK* (DMA read)
10
30
ns
t
28
23
25
Inactive time, DMAACK* (DMA read/write)
10
ns
t
29
23
25
Hold time, DMAREQ* rising edge after
DMAACK* falling edge (DMA read/write)
10
1 CLK
+
15
ns
t
30
25
Hold time, DMAACK* active (DMA write)
2.5 CLK
t
31
25
Delay, data valid after falling edge DMAACK* (DMA write)
1.5 CLK
NOTES:
1. Timing numbers for RESET* and CLK are valid for both asynchronous and synchronous specifications. The device will
operate on any clock with a 40
–
60 or better duty cycle.
2. On host-I/O cycles, immediately following SVCACK* cycles and writes to EOSRR, DTACK* will be delayed by 20 CLKs (1 ms
@ 20 MHz; 800 ns @ 25 MHz). On systems that do not use DTACK* to signal the end of the I/O cycle, wait states or some
other form of delay generation must be used to assure that the CD1283 is not accessed until after this time period.
3. As TCLK increases, device performance decreases. A minimum clock frequency of 25 MHz is required to guarantee specified
performance. The recommended maximum TCLK is 1000 ns.
4. DTACK* sources current (drives
‘
high
’
) until the voltage on the DTACK* line is approximately 1.5 V; then DTACK* goes to the
‘
open-drain
’
(high-impedance) state.
Figure 17. Reset Timing
Table 12. Asynchronous Timing Reference Parameters
(Sheet 2 of 2)
Timing
No.
Figure
Parameter
MIN
MAX
Unit
t
1
V
CC
CLK
RESET*
t
a
t
b
C2
C1
C2
C1
C2
CLK/2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD1284 | IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports |
| CD13002 | NPN SILICON PLANAR EPITAXIAL, HIGH VOLTAGE FAST SWITCHING POWER TRANSISTOR |
| CD14538 | CMOS DUAL PRECISION MONOSTABLE MULTIVIBRATOR |
| CD14538BMS | CMOS Dual Precision Monostable Multivibrator |
| CD15B-15MB | CD105B |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD1284 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports |
| CD-12AFFM-QL8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10 |
| CD-12AFFM-QR8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10 |
| CD-12AMMM-QL8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10 |
| CD-12BFFA-LL7001 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。