參數(shù)資料
型號(hào)： CD1283
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface
中文描述： 符合IEEE 1284兼容并行接口
文件頁(yè)數(shù)： 16/94頁(yè)
文件大小： 1237K
代理商： CD1283
CD1283
—
IEEE 1284-Compatible Parallel Interface
16
Datasheet
3.3
Pin Descriptions
Symbol
Pin No.
Type
Description
(Sheet 1 of 3)
A[6:0]
84
–
90
I
ADDRESS BUS:
Together with CS* or one of the SVCACK* inputs and DS*, this input
selects an on-chip register for a read or write operation or an acknowledgment to a
service request.
BYTESWAP
82
I
BYTESWAP:
This input determines the byte order for 2-byte DMA transfers and for
writes to the DMABUF register.
If BYTESWAP is set to
‘
1
’
, Data Bus bits 15:8 are driven with the byte transferred first
on the parallel port bus. Data Bus bits 7:0 are driven with the byte transferred second
on the parallel port bus. If BYTESWAP is set to
‘
0
’
, the data order is reversed, bits 7:0
are driven with the first byte transferred, and bits 15:8 are driven with the second byte
transferred.
CLK
73
I
SYSTEM CLOCK:
This input has a 25 MHz maximum; 16 MHz is the recommended
minimum for satisfactory device performance.
CLK/2
80
O
SYSTEM CLOCK DIVIDED BY TWO OUTPUT:
This signal is equivalent to the internal
operating clock of the device.
CS*
78
I
ACTIVE-LOW CHIP SELECT:
When active, the input CS* in conjunction with DS*,
initiates a I/O cycle with the CD1283. CS* must be set to
‘
1
’
during DMA read/write
operations.
DB[15:0]
92
–
99, 2
–
9
I/O
BIDIRECTIONAL DATA BUS [15:0]:
Only DMA transfers and writes to the DMA Buffer
register are true 16-bit operations. During all register writes other than to the DMA
Buffer register, only bits 7:0 are written to the addressed register. Register reads
duplicate the register contents on both the lower byte, bits 7:0, and upper byte, bits
15:8.
DS*
77
I
ACTIVE-LOW DATA STROBE:
During an active I/O cycle, the input DS* strobes data
into on-chip registers on write cycles or enables data onto the data bus during read
cycles. DS* is ignored during DMA operations.
DTACK*
75
AR
ACTIVE-LOW DATA TRANSFER ACKNOWLEDGE:
This output indicates: when the
device has completed the requested I/O operation, and when the cycle may finish. This
signal can be used to implement wait-state insertion for the local CPU. It is an Active
Release output, driving to logic
‘
1
’
then releasing to OD. DTACK* must be tied to
external V
CC
with a pull-up resistor. DTACK* is not activated on DMA cycles.
OUTEN
83
I
OUTPUT ENABLE:
This pin must be set to
‘
1
’
to enable output pin functions. When
OUTEN is set to
‘
0
’
, it forces all pins that can act as outputs to remain in a tristate
condition.
OUTEN is used as a test input and is not normally used in an end application. User
designs should tie this pin to V
CC
through a pull-up resistor.
RESET*
79
I
ACTIVE-LOW RESET INPUT:
Initializes the device to the default condition. All internal
registers are set to their reset condition and all transfer operations are set to the default
state.
R/W*
76
I
READ/WRITE*:
This pin must be set to
‘
1
’
for a register read operation and set to
‘
0
’
for a register write operation. This input is ignored for DMA operations.
DMAREQ*
13
O
ACTIVE-LOW DMA REQUEST:
When the internal control bit DMAen is set, the output
DMAREQ* is asserted whenever internal FIFO conditions warrant a DMA transfer.
DMAREQ* is deasserted on the falling edge of DMAACK* when DMA transfers must
not continue past the current transfer.
DMAACK*
12
I
ACTIVE-LOW DMA ACKNOWLEDGE:
This signal must never be asserted unless in
response to a DMAREQ* from the device. DMAACK* is the only bus handshake signal
recognized during a DMA transfer. (CS* must be high whenever DMAACK* is
asserted.) The direction of the DMA transfer is determined by the internal control bit
DMAdir.
相關(guān)PDF資料
PDF描述
CD1284 IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
CD13002 NPN SILICON PLANAR EPITAXIAL, HIGH VOLTAGE FAST SWITCHING POWER TRANSISTOR
CD14538 CMOS DUAL PRECISION MONOSTABLE MULTIVIBRATOR
CD14538BMS CMOS Dual Precision Monostable Multivibrator
CD15B-15MB CD105B
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CD1284 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
CD-12AFFM-QL8D01 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10
CD-12AFFM-QR8D01 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10
CD-12AMMM-QL8D01 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10
CD-12BFFA-LL7001 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*