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參數(shù)資料
| 型號： | CD1283 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface |
| 中文描述： | 符合IEEE 1284兼容并行接口 |
| 文件頁數(shù)： | 63/94頁 |
| 文件大?。?/td> | 1237K |
| 代理商： | CD1283 |
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IEEE 1284-Compatible Parallel Interface
—
CD1283
Datasheet
63
7.3.9
Parallel FIFO Empty Pointer Register
This register contains the internal empty location pointer of the FIFO. It identifies the location in
the FIFO from which the next byte of data will transfer from the FIFO.
The PFEP register is cleared by a device or FIFO reset.
7.3.10
Parallel FIFO Fill Pointer Register
This register holds the internal fill location pointer of the FIFO. It identifies the location in the
FIFO to receive the next data byte from the pipeline.
The PFFP register is cleared by a device or FIFO reset.
7.3.11
Parallel FIFO Holding Registers
2
Set Tag:
This bit specifies that the next character written to the parallel channel through the PFHR1 is to be tagged
as an ECP or EPP special character. This bit is cleared by the write to PFHR1, thus this bit must be set each time a
tagged character is to be written.
1
Error Interrupt Enable:
This bit enables a non-zero DataErr status to cause an interrupt (if IntEn is also set).
0
DMA Buffer Write Enable:
This bit must be set to enable host writes to the DMABUF register. It also enables the
FIFO data pipeline to empty DMABUF when it has been written to by the host system. In this case, the system will
write to the DMA buffer and not use DMA transfers, providing a low-performance alternative to DMA transfers.
Bit
Description (Continued)
(Sheet 2 of 2)
Register Name: PFEP
Register Description: Parallel FIFO Empty Pointer
Access: R/W
8-Bit Hex Address: 39
Default Value: 00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
6-Bit Binary FIFO Pointer Value
Register Name: PFFP
Register Description: Parallel FIFO Fill Pointer
Access: R/W
8-Bit Hex Address: 38
Default Value: 00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
6-Bit Binary FIFO Pointer Value
Register Name: PFHR1
Register Description: Parallel FIFO Holding Register 1
Access: R/W
8-Bit Hex Address: 35
Default Value: 00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
8-Bit Character Data
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CD1284 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports |
| CD-12AFFM-QL8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10 |
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