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參數(shù)資料
| 型號： | CD1283 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface |
| 中文描述： | 符合IEEE 1284兼容并行接口 |
| 文件頁數(shù)： | 40/94頁 |
| 文件大?。?/td> | 1237K |
| 代理商： | CD1283 |
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CD1283
—
IEEE 1284-Compatible Parallel Interface
40
Datasheet
5.5.10
Data Transfers
In Compatibility mode, incoming HstClk (STROBE*) pulses activate PerBsy (BUSY), and the data
on PD[7:0] is held in latches. PerBsy protects the data latches by signalling the master it is not
ready for more transfers. After the HstClk pulse ends, a pulse is sent on PerClk (ACK*) to
acknowledge the receipt of the data into the holding latches. After the data moves from the latches
to the FIFO, PerBsy goes low to signal readiness for the next character.
All other data transfer modes require IEEE-1284 negotiations.
5.5.11
Compatibility Mode Status
The IEEE 1284 specification requires that the three Compatibility mode status lines (SELECT,
FAULT*, and PError) must not be asserted unless PerBsy (BUSY) is high. PerBsy can only be
activated in response to a received character, and must remain high until the status condition (for
example, paper out) changes.
To send these status signals to the master device, set the SetPs bit (SCR[2]) and the appropriate bit
in the OVR for each of the status signals. The SetPs bit activates PerBsy, which remains active until
ClrPs (SCR[3]) is set. No data is lost in this operation.
5.6
IEEE 1284 Parallel Protocol Support
5.6.1
Compatibility Mode
Compatibility mode provides backward compatibility with Centronics and PC-compatible printer
interfaces. When the host parallel port is in Compatibility mode (with no data transfer in progress),
the host can initiate data transfers in Compatibility mode or initiate negotiations to a new operating
mode.
Only Busy-while-Strobe and Ack-in-Busy timing is supported in Compatibility mode. Busy-after-
Strobe, Ack-after-Busy, and Ack-while-Busy timings are not supported.
5.6.2
Reverse-Nibble and Reverse-Byte Modes
These modes support reverse transfers only, from slave to master. Reverse-Nibble mode is enabled
with NER[0]; Reverse-Byte mode is enabled with NER[1]. Reverse-Nibble mode sends 4 bits at a
time over four of the peripheral status lines. With software drivers the advantage of this scheme is
that any unidirectional PC parallel port can be used for bidirectional data transfers. Reverse-Byte
mode requires bidirectional buffers on the PC hardware, but allows substantially faster transfers
because it moves one byte at a time.
Figure 9. Supported Compatibility Mode Timing
nStrobe
nAck
BUSY
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CD1284 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports |
| CD-12AFFM-QL8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10 |
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