參數(shù)資料
型號(hào)： CD1283
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface
中文描述： 符合IEEE 1284兼容并行接口
文件頁(yè)數(shù)： 54/94頁(yè)
文件大?。?/td> 1237K
代理商： CD1283
CD1283
—
IEEE 1284-Compatible Parallel Interface
54
Datasheet
7.1.3
General-Purpose I/O Direction Register
7.1.4
General-Purpose I/O Register
The GPDIR and GPIO registers enable access and control of the General-Purpose I/O port. The
General-Purpose I/O port provides a byte-wide general purpose set of signals that are individually
direction programmable.
The GPIO register accesses the data port on pins 53
–
60 (G[7:0]) with Data0 accessing GP[0], and
so on. The corresponding bit in the GPDIR controls the direction of the associated signal; a logic
‘
1
’
programs the signal as output, and a logic
‘
0
’
programs it as input.
When writing to the GPIO register,
‘
1
’
s and
‘
0
’
s are reflected in their true states on the pins that are
programmed as outputs. When reading from the GPIO register, bits programmed as inputs reflect
the true state of the signal condition on those bits; bits programmed as output will reflect the
previously set state.
7.1.5
Parallel Interrupt Register
The PIR indicates the source of service requests being presented by the parallel channel, either
from the parallel port or from the pipeline.
Register Name: GPDIR
Register Description: General-Purpose I/O Direction
Access: R/W
8-Bit Hex Address: 71
Default Value: 00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Dir7
Dir6
Dir5
Dir4
Dir3
Dir2
Dir1
Dir0
Register Name: GPIO
Register Description: General-Purpose I/O
Access: R/W
8-Bit Hex Address: 70
Default Value: 00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data7
Data6
Data5
Data4
Data3
Data2
Data1
Data0
Register Name: PIR
Register Description: Parallel Interrupt
Access: R/W
8-Bit Hex Address: 61
Default Value: 00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PPireq
PPort
Pipeline
0
0
0
0
0
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