- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379802 > CD1283 (Intel Corp.) IEEE 1284-Compatible Parallel Interface PDF資料下載
參數(shù)資料
| 型號： | CD1283 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface |
| 中文描述： | 符合IEEE 1284兼容并行接口 |
| 文件頁數(shù)： | 66/94頁 |
| 文件大?。?/td> | 1237K |
| 代理商： | CD1283 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁當前第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁
CD1283
—
IEEE 1284-Compatible Parallel Interface
66
Datasheet
7.3.15
Run-Length Count Register
This register works with PFHR1 and PFHR2 to perform run-length encoding/decoding when the
RLEen bit (PFCR[3]) is set (the parallel port must be in ECP mode; in other modes, run-length
encoding will not occur).
In the transmit direction, strings of three or more identical characters are recognized and
compressed. The running count of identical characters is kept in the RLCR. Once the sequence is
broken by a different character or the end of the transmit burst transfer, the count and a single copy
of the duplicated character are put in the FIFO.
In the receive direction, run-length codes can be received from the remote device. These codes are
recognized
‘
on the fly
’
as data flows from the FIFO through the Holding register pipeline. A run-
length code is diverted to the RLCR. The subsequent character from the FIFO is duplicated (held in
PFHR1) while the RLCR is decremented. Once the RLCR reaches zero, normal pipeline data
movement is resumed. If run-length codes are being received by the parallel port but RLEen is not
set, the codes will enter PFHR1 and PFHR2 as tagged data and cause interrupts to the host. The
host must directly read the tagged Holding register to remove the character from the pipeline and
clear the tag.
7.3.16
Stale Data Timer Count Register
This register determines the period used to signal stale data in the FIFO. The timer is used only in
the receive direction. Each time a new character is placed in the FIFO from the parallel port, the
SDTCR is reloaded from the SDTPR and down-counting begins at the tick rate. If the counter
reaches zero, the Stale bit (PFSR[2]) is set. If the amount of data available is greater than or equal
to one word, a DMA request is made to move all remaining whole words to the host by DMA
transfer. Once the DMA transfer is complete, a single remaining character causes an interrupt to the
host to remove the character by reading PFHR2.
This register is cleared by device or FIFO reset. Clearing it manually causes the Stale bit to be true.
Register Name: RLCR
Register Description: Run-Length Count
Access: R/W
8-Bit Hex Address: 37
Default Value: 00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
7-Bit Unsigned Binary Count
Register Name: SDTCR
Register Description: Stale Data Timer Count
Access: R/W
8-Bit Hex Address: 3D
Default Value: 00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
8-Bit Stale Data Timer Count
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD1284 | IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports |
| CD13002 | NPN SILICON PLANAR EPITAXIAL, HIGH VOLTAGE FAST SWITCHING POWER TRANSISTOR |
| CD14538 | CMOS DUAL PRECISION MONOSTABLE MULTIVIBRATOR |
| CD14538BMS | CMOS Dual Precision Monostable Multivibrator |
| CD15B-15MB | CD105B |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD1284 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports |
| CD-12AFFM-QL8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標準包裝:10 |
| CD-12AFFM-QR8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標準包裝:10 |
| CD-12AMMM-QL8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標準包裝:10 |
| CD-12BFFA-LL7001 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標準包裝:10 |
發(fā)布緊急采購，3分鐘左右您將得到回復。