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參數(shù)資料
| 型號： | CD1283 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface |
| 中文描述： | 符合IEEE 1284兼容并行接口 |
| 文件頁數(shù)： | 70/94頁 |
| 文件大?。?/td> | 1237K |
| 代理商： | CD1283 |
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CD1283
—
IEEE 1284-Compatible Parallel Interface
70
Datasheet
Any change in the mode of the parallel port is reported to the peripheral host by interrupt if the
NegCh bit is set in the PCIER; host software then reads the NSR to determine the current status and
condition. Once the host has read the NSR status resulting from the current negotiation, it should
clear the register in preparation for additional negotiation cycles. The NSR can be cleared by
writing any value.
7.4.6
Ones Detect Register
Setting the bits in this register enables the CD1284 to generate an interrupt
–
if SigCh (PCIER[4])
is set
–
when the selected signal changes from low to high (rising edge). Bits 7:4 are reserved and
must be written as zeros; they return zero when read. The settings in this register have no effect
(that is, SigCh interrupt is not generated) unless the device is in Manual mode.
7.4.7
Output Value Register
This register controls output signals. In Manual mode, all signals are controlled by these register
settings. In Compatibility and EPP modes, PerBsy and PerClk are controlled by the internal
parallel port state machine while AkDaRq, xFlag, and nDataAv are controlled by this register. In
ECP mode, the settings in this register have no effect.
Register Name: ODR
Register Description: Ones Detect
Access: R/W
8-Bit Hex Address: 2D
Default Value: 00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
A1284
nInit
HstBsy
HstClk
Register Name: OVR
Register Description: Output Value
Access: Write only
8-Bit Hex Address: 2B
Default Value: 48
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PerBsy
PerClk
AkDaRq
XFlag
nDatAv
0
0
0
Bit
Description
7
Peripheral Busy:
User-controlled in Manual mode only.
6
Peripheral Clock:
User-controlled in Manual mode only.
5
Acknowledge Data Request:
In Compatible mode, this signal is the PError (Peripheral Error) signal.
In EPP mode, this signal is auxiliary and is a user-defined signal (USER 1).
4
XFlag:
In Compatible mode, this signal is the SELCT (Select) signal.
In EPP mode, this signal is auxiliary and is a user-defined signal (USER 2).
3
Negative-true Data Available:
In Compatible mode, this signal is the nFault (negative-true fault) signal.
In EPP mode, this signal is auxiliary and is a user-defined signal (USER 3).
2:0
Reserved:
These bits must be written as
‘
0
’
.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CD1284 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports |
| CD-12AFFM-QL8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標準包裝:10 |
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