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參數(shù)資料
| 型號(hào)： | CD1283 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface |
| 中文描述： | 符合IEEE 1284兼容并行接口 |
| 文件頁數(shù)： | 31/94頁 |
| 文件大小： | 1237K |
| 代理商： | CD1283 |
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IEEE 1284-Compatible Parallel Interface
—
CD1283
Datasheet
31
A direction change (DirCh) interrupt occurs when the remote master has reversed the interface
from ECP forward to ECP reverse or ECP reverse to ECP forward. The IDReq interrupt is
generated when the remote master issues an ID Request command during IEEE 1284 negotiations.
The normal response by the local CPU is to send its ID string after reversing the direction of the
data pipeline by setting the DMAdir bit to
‘
1
’
.
If vectored interrupts are required by the system, then the LIVR must be initialized by the local
CPU. The upper five bits are defined by the local CPU and can be any value appropriate to the
system design. The lower three bits should be initialized to zero during the programming of the
LIVR, however they are
‘
don
’
t cares
’
and masked in the PIVR to provide the vector indicating the
source, and type of request from the parallel channel.
Access to the parallel channel LIVR is made by first setting the AER to
‘
x
’
00
’
, making the Channel
Zero register set accessible. Since the LIVR is a read/write register, the local CPU can read it at any
time. When read during a normal read cycle, the upper 5 bits return the original value loaded by the
CPU.
The three least-significant bits always ready back as the current service-request status of the
parallel port if an interrupt is in progress; otherwise they read back as
‘
0
’
. The encoding of the three
least-significant bits of LIVR during a service acknowledge cycle indicates which of the functional
blocks in the parallel channel is requesting service as shown in the following table.
Figure 6. Control Signal Generation
DGRANT*
CD1283
CS*
R/W*
DS*
AD[6:0]
DB[7:0]
SVCACKP*
CPU
ADDRESS
CPU I/O
CONTROL
ADDRESS
DECODE
LOGIC
CPU
DATA
Table 6. LIVR[2:0] Encoding
IT2
IT1
IT0
Requestor
1
0
0
Channel control state machine
1
0
1
Data pipeline
1
1
0
Both
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD1284 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports |
| CD-12AFFM-QL8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10 |
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