
LIST OF FIGURES
S1C38000 TECHNICAL MANUAL
EPSON
v
List of Figures
Figure 3-1
S1C38000 Internal Block Diagram ..................................................................................... 5
Figure 3-2
Typical System Implementation .........................................................................................6
Figure 3-3
3.3V Only CompactFlash Support...................................................................................... 7
Figure 3-4
Generic Bus Interface......................................................................................................... 8
Figure 3-5
Example 1 Memory Configuration ...................................................................................... 9
Figure 3-6
Example 2 Memory Configuration ..................................................................................... 10
Figure 3-7
USB Interface .................................................................................................................... 11
Figure 3-8
UART / IrDA Interface ....................................................................................................... 11
Figure 3-9
SPI Master Interfaced to ADS7846 Touch-Screen Controller ........................................... 12
Figure 3-10
Passive LCD Panel Interface ............................................................................................ 12
Figure 3-11
TFT/D-TFD Panel Interface............................................................................................... 12
Figure 3-12
HR-TFT Panel Interface .................................................................................................... 13
Figure 4-1
S1C38000 Pin-Out (QFP-208pin) ..................................................................................... 14
Figure 4-2
S1C38000 Pin-Out (CFLGA-239pin Bottom Side View) .................................................. 15
Figure 6-1
Generic Bus Interface Read Timing .................................................................................. 29
Figure 6-2
Generic Bus Interface Write Timing .................................................................................. 31
Figure 6-3
CompactFlash Interface Attribute Mode Read Timing ...................................................... 32
Figure 6-4
CompactFlash Interface Attribute Mode Write Timing....................................................... 33
Figure 6-5
CompactFlash Interface Memory Read Timing................................................................. 34
Figure 6-6
CompactFlash Interface Memory Write Timing ................................................................. 35
Figure 6-7
CompactFlash Interface I/O Mode Read Timing ............................................................... 36
Figure 6-8
CompactFlash Interface I/O Mode Write Timing ............................................................... 37
Figure 6-9
CompactFlash Interface No Wait-State Memory Read Timing ......................................... 38
Figure 6-10
CompactFlash Interface No Wait-State Memory Write Timing.......................................... 39
Figure 6-11
CompactFlash Interface No Wait-State I/O Mode Read Timing........................................ 40
Figure 6-12
CompactFlash Interface No Wait-State I/O Mode Write Timing........................................ 41
Figure 6-13
Data Signal Rise and Fall Time......................................................................................... 42
Figure 6-14
Differential Data Jitter........................................................................................................ 42
Figure 6-15
Differential to EOP Transition Skew and EOP Width ........................................................ 42
Figure 6-16
Receiver Jitter Tolerance .................................................................................................. 43
Figure 6-17
SPI1 Interface Timing........................................................................................................ 44
Figure 6-18
SPI2 Interface Timing........................................................................................................ 45
Figure 6-19
SRAM/ROM/FLASH Memory/External Device Timing ...................................................... 46
Figure 6-20
SDRAM Init and LMR Timing ............................................................................................48
Figure 6-21
SDRAM Single Read Timing .............................................................................................49
Figure 6-22
SDRAM Single Write Timing ............................................................................................. 50
Figure 6-23
SDRAM Burst Read Timing............................................................................................... 51
Figure 6-24
SDRAM Burst Write Timing............................................................................................... 52
Figure 6-25
SDRAM Auto Refresh Timing............................................................................................53
Figure 6-26
SDRAM Self Refresh Timing............................................................................................. 54
Figure 6-27
RESET# Timing................................................................................................................. 55
Figure 6-28
PORST# Timing ................................................................................................................ 55
Figure 6-29
PWMOUT Timing .............................................................................................................. 56
Figure 6-30
Passive/TFT Power-On Sequence Timing ........................................................................ 57
Figure 6-31
Passive/TFT Power-Off Sequence Timing ........................................................................ 58
Figure 6-32
Power Save Status Timing ................................................................................................ 59
Figure 6-33
Panel Timing Parameters.................................................................................................. 60
Figure 6-34
Generic STN Panel Timing................................................................................................ 61