
20 UART 2
S1C38000 TECHNICAL MANUAL
EPSON
187
bit 7
Receive FIFO Error
This flag indicates that a receiver FIFO error (parity error, framing error, or break
indication) has occurred. This bit remains set as long as at least one character in the
FIFO has an error in it.
Notes: Flushing the Receive FIFO when this bit is set to 1 will result in this bit locking at 1, only
a system reset will then clear the bit.
If an error occurs in the first character sent to the FIFO the Receive FIFO Error flag will
be set but the detailed error flag, URT2[14h] bits [3:0], will not be set.
bit 6
Transmit Empty
In FIFO mode, this flag indicates that the transmitter FIFO and the shift register are both
empty. In non-FIFO mode, this flag indicates that the Transmit Holding register and the
shift register are both empty.
bit 5
Transmit Holding Register Empty
In FIFO mode, this flag indicates that the transmitter FIFO is empty. In non-FIFO mode,
this flag indicates that the Transmit Holding register is empty. If the Transmit Holding
register empty interrupt is enabled, then UART2 will generate an interrupt request. This
bit is set only after the transmit holding register or the transmit FIFO is emptied by
transmission, not by any other means (i.e. reset, flush, etc.).
bit 4
Break Interrupt Flag
This flag indicates that the received data input is held to a logic 0 for the during of the
character transmission. In FIFO mode, this error is associated with the particular
character in the FIFO it applies to. This error is revealed when its associated character is
at the top of the FIFO. If the Receiver Line Status interrupt is enabled UART2 will
generate an interrupt request.
bit 3
Framing Error
This flag indicates that the receiver does not detect a valid stop bit in the receiver
character. In FIFO mode, this error is associated with the particular character in the
FIFO it applies to. This error is revealed when its associated character is at the top of the
FIFO. If the Receiver Line Status interrupt is enabled UART2 will generate an interrupt
request. This bit is cleared when the Line Status Register is read.
bit 2
Parity Error
This flag indicates a parity error in the receiver provided the parity enable bit is set. In
FIFO mode, this error is associated with the particular character in the FIFO it applies
to. This error is revealed when its associated character is at the top of the FIFO. If the
Receiver Line Status interrupt is enabled UART2 will generate an interrupt request. This
bit is cleared when the Line Status Register is read.
bit 1
Overrun Error
In non-FIFO mode, this flag indicates that a new character arrived in the receiver before
the current character in the Receive Buffer register is read. In FIFO mode, this flag
indicates that a new character arrived in the receiver when the FIFO is full. If the
Receiver Line Status interrupt is enabled UART2 will generate an interrupt request. This
bit is cleared when the Line Status Register is read.
Line Status Register
URT2[14h]
Default = 0000 0000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
n/a
Receive
FIFO
Error
Transmit
Empty
Transmit
Holding
Register
Empty
Break
Interrupt
Framing
Error
Parity
Error
Overrun
Error
Data
Ready
15
14
13
12
11
10
9876543210