
26 USB
S1C38000 TECHNICAL MANUAL
EPSON
241
26 USB
26.1 Overview
The S1C38000 contains a USB Client that is USB Specification Version 1.0/1.1 compliant. It is
Vendor Specific Class.
The USB device supports bulk, isochronous, control, and interrupt data transfers between the
S1C38000 and a USB host. The USB client contains independent 64-byte transmit and receive
FIFOs to maximize throughput.
The bus interface between the ARM720T and the USB supports CPU-controlled transfers, interrupts
and DMA transfers.
26.2 Register Descriptions
The default base address for the USB registers is F8000600h. All non-reserved register bits default
to 0 unless specified otherwise.
bit 6
Software EOT
This bit determines the response to an IN request to Endpoint 4 when the transmit FIFO
is empty. If either this bit or the DMA EOT# input signal are asserted, the S1C38000
responds to an IN request to Endpoint 4 with an ACK and a zero length packet if the
FIFO is empty. If neither this bit nor the DMA EOT# signal are asserted, the USB
Device responds to an IN request from Endpoint 4 with an NAK if the FIFO is empty,
indicating that it expects to transmit more data. This bit can be cleared by an I/O write
with a data value of 0. It is automatically cleared when the USB Device responds to the
host with a zero length packet when the FIFO is empty.
bit 5
USB Enable
Any device or configuration descriptor reads from the host will be acknowledged with a
NAK until this bit is set. This allows time for the local CPU to set up the interrupt
polling register, maximum packet size registers, and other configuration registers (e.g.
Product ID and Vendor ID) before the host reads the descriptors.
Note: The USB device and configuration descriptors cannot be read by the USB host until the
USB Enable bit is set. Until then, the device enumeration process cannot complete, so
the device will not be recognized by the USB host.
bit 4
Endpoint 4 Stall
If this bit is set, host bulk reads from the transmit FIFO will result in a STALL
acknowledge by the S1C38000. No data will be returned to the USB host.
bit 3
Endpoint 3 Stall
If this bit is set, host bulk writes to the receive FIFO will result in a STALL
acknowledge by the S1C38000. Receive data will be discarded.
bit 2
DMA Request
This status bit reflects the state of the internal USB DMA request signal, and allows the
S1C38000 to monitor DMA transfers.
DMA Control Register
USB[00h]
Default = 0000 0000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
n/a
Software
EOT
USB
Enable
Endpoint
4 Stall
Endpoint
3 Stall
DMA
Request
DMA
Request
Enable
DMA
Direction
15
14
13
12
11
10
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